Application of HT-PSM to 180-nm logic devices

Yasutaka Kikuchi; Takashi Seno; Kensuke Kawanabe; Eiji Bunki; Yuki Otsuka; Yoshiro Yamada

doi:10.1117/12.332876

18 December 1998 Application of HT-PSM to 180-nm logic devices

Yasutaka Kikuchi, Takashi Seno, Kensuke Kawanabe, Eiji Bunki, Yuki Otsuka, Yoshiro Yamada

Proceedings Volume 3546, 18th Annual BACUS Symposium on Photomask Technology and Management; (1998) https://doi.org/10.1117/12.332876
Event: 18th Annual BACUS Symposium on Photomask Technology and Management, 1998, Redwood City, CA, United States

Abstract

Currently various techniques, such as OPC, Beam proximity correction, are under development aiming at volume production of 180 nm logic devices. 180 nm lithography requires to handle critical dimensions below the light wavelength of stepper, HT- PSM is considered to be a potential solution for securing a certain process margin, and it is the case not only for 'hole' patterns but for 'line' patterns. On 180 nm device, since the CD on reticle is sub-micron, uniformity control across iso- dense area and CD linearity become very difficult compared with simple cell-repeating patterns like memory devices. Here, under the assumption that we apply MoSiON HT-PSM to 'line' pattern of 180 nm device, we will report various evaluation results which are mainly related to mask making process. The conclusion is that HT-PSM has advantages over binary mask when it is applied for 'line' patterns, and we could fulfill those reticle requirements by optimizing conditions of materials, dry-etcher, writing tools and beam/resist combination.

Citation Download Citation

Yasutaka Kikuchi, Takashi Seno, Kensuke Kawanabe, Eiji Bunki, Yuki Otsuka, and Yoshiro Yamada "Application of HT-PSM to 180-nm logic devices", Proc. SPIE 3546, 18th Annual BACUS Symposium on Photomask Technology and Management, (18 December 1998); https://doi.org/10.1117/12.332876

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