Impact of silicon-type floating gate on EEPROM performance

Karine Ogier-Monnier; Philippe Boivin; Olivier Bonnaud

doi:10.1117/12.323973

4 September 1998 Impact of silicon-type floating gate on EEPROM performance

Karine Ogier-Monnier, Philippe Boivin, Olivier Bonnaud

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323973
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

In CMOS technology for EEPROM, refractory metal silicide is currently used to shunt the doped polysilicon layer for the floating gate electrode. Due to their manufacturability, tungsten silicide (WSi₂) and tantalum silicide (TaSi₂) are widely used in integrated circuit manufacturing. In this paper, electrical tests are performed on MOS capacitors and on memory cells. We will compare three types of silicides: TaSi₂ deposited by sputtering and WSi₂ deposited with two chemistries: the monosilane reduction of tungsten hexafluoride (MS) and the dichlorosilane reduction of tungsten hexafluoride (DCS). Regarding the cycling performance of the memory cell, tantalumsilicide and tungsten silicide DCS are both good candidates for gate material, but in term of data retention results, they are not the best candidates because of their higher charge loss during bake.

Citation Download Citation

Karine Ogier-Monnier, Philippe Boivin, and Olivier Bonnaud "Impact of silicon-type floating gate on EEPROM performance", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323973

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