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Gate insulator/stack scaling is arguably one of the most challenging aspects of device scaling. As gate lengths are scaled into the sub-100 nm regime, alternate materials other than SiO2 will be needed to continue device scaling. The SIA roadmap has called for introduction of high-k materials below the 100 nm technology node due to problems with direct tunneling in SiO2. However, introduction of high-k poses many challenges in the process/materials side in CMOS process integration. Also, there are device scaling issues that are equally important. When k is increased beyond a certain level, unforeseen effects come to play. A phenomenon known as fringing-induced barrier lowering (FIBL) increases Ioff and degrades the subthreshold swing of the device. This paper describes this phenomenon, and provides insight into device scaling with high k materials. A host of other tradeoffs, especially those concerning control of Ioff and speed, are examined using 2-D simulator and analytical models. Suggestions to control FIBL are also detailed.
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