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10 March 2020 Towards a Si foundry-compatible GaN-on-Si MMIC process on 200mm Si with Cu damascene BEOL (Conference Presentation)
Jeffrey LaRoche
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Proceedings Volume 11280, Gallium Nitride Materials and Devices XV; 112801G (2020) https://doi.org/10.1117/12.2543913
Event: SPIE OPTO, 2020, San Francisco, California, United States
Abstract
In 2013 Raytheon began to integrate submicron (≤0.25 µm gate) 200mm GaN on Si HEMT processes within a commercial CMOS Si Foundry environment. When fully realized, these processes will demonstrate multi GHz GaN on Si MMICs by leveraging a fully subtractively processed transistor coupled with multi-level copper based back end of line (Cu BEOL) processes. This work provides a status update on the progress towards that goal.
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Jeffrey LaRoche "Towards a Si foundry-compatible GaN-on-Si MMIC process on 200mm Si with Cu damascene BEOL (Conference Presentation)", Proc. SPIE 11280, Gallium Nitride Materials and Devices XV, 112801G (10 March 2020); https://doi.org/10.1117/12.2543913
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KEYWORDS
Silicon
Back end of line
Copper
Gallium nitride
Field effect transistors
Transistors
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