Unspecified Zuan Khalik Profile

Zuan Khalik

at ASML Netherlands BV

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Publications (2)

Proceedings Article | 10 April 2024 Presentation + Paper

Feature grouping to enable edge placement error-aware process control in multi-feature logic use case

Guillaume Schelcher, Marsil Athayde, Stijn Schoofs, Jeff Hsia, Zuan Khalik, Fahong Li, Konstantin Nechaev, Reza Sahraeian, Amir-Hossein Tamaddon, Victor Blanco, Stefan van der Sanden, Yichen Zhang, Roy Anunciado, Harm Dillen, Philippe Leray

Proceedings Volume 12955, 129550O (2024) https://doi.org/10.1117/12.3010421

KEYWORDS: Semiconducting wafers, Overlay metrology, Cross validation, Process control, Logic, Metrology, Simulations, Scanning electron microscopy, Lithography

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Proceedings Article | 30 April 2023 Presentation

The edge placement error characterization and optimization for advanced logic and DRAM nodes

Harm Dillen, Wim Tel, Jaap Karssenberg, Jan Mulkens, Roy Anunciado, Yichen Zhang, Konstantin Nechaev, Zuan Khalik

Proceedings Volume 12496, 124960O (2023) https://doi.org/10.1117/12.2658832

KEYWORDS: Overlay metrology, Logic, Optical proximity correction, Metrology, Stochastic processes, Semiconductors, Semiconductor manufacturing, Scanners, Manufacturing, Line edge roughness

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