As the semiconductor industry advances to smaller design rules, Photoresist performance is critical for the
tight lithography process. Critical Dimension (CD), Side Wall Angle (SWA) and Photoresist height,
which are critical for the final semiconductor patterning, depend on the Photoresist chemistry. Each
Photoresist batch has to be qualified to verify that it can achieve the required quality specifications.
Photoresist qualification is done by exposing Photoresist and monitoring outcome after developing.
In this work, Archer 300LCM scatterometry-based Optical CD (OCD) was evaluated using Dow 193
Immersion Top Coat Free Photoresist and Anti Reflection Layers (ARL). As part of the sensitivity
analysis, changes in Photoresist thickness, ARL thickness and Photoresist formulation were evaluated.
Results were compared to CD-SEM measurements. The CD sensitivity was evaluated on two grating
dense line and space features with nominal Middle CD (MCD) values of 37nm and 75nm. Sensitivity of
the OCD for Photoresist parameters was demonstrated.
As the semiconductor industry continues to drive toward smaller design nodes, overlay error budgets will continue to
shrink making metrology ever more challenging. Moreover, this challenge is compounded by the need to continue to
drive down costs and increase productivity, especially given the competitive and macro-economic landscape going
forward. In order to satisfy these two contradicting requirements, new ways of maintaining metrology tools and recipes
are needed. Traditionally, recipes are generated manually by operators or even metrology engineers, involving both tool
time and engineering resources. Furthermore, the influence of individual skill levels can lead to undesirable variations
and is a potential source of errors that could result in yield loss. By means of automatic recipe generation both
engineering and capital equipment resources can be minimized. Implementation of an automated recipe creation process
will also result in improved recipe integrity. In this study, we show a methodology of a highly automated recipe
generation for overlay measurements. We will outline the benefits of such an implementation and comment on the value
for all segments of the semiconductor industry as well as provide data from production fabs demonstrating these
capabilities and benefits.
Layer to layer alignment in optical lithography is controlled by feedback of scanner correctibles provided by analysis
of in-line overlay metrology data from product wafers. There is mounting evidence that the "high order" field
dependence, i.e. the components which contribute to residuals in a linear model of the overlay across the scanner field
will likely need to be measured in production scenarios at the 45 and 32 nm half pitch nodes. This is in particular
true in immersion lithography where thermal issues are likely to impact intrafield overlay and double pitch patterning
scenarios where the high order reticle feature placement error contribution to the in-die overlay is doubled.
Production monitoring of in-field overlay must be achieved without compromise of metrology performance in order to
enable sample plans with viable cost of ownership models. In this publication we will show new results of in-die
metrology, which indicate that metrology performance comparable with standard scribeline metrology required for the
45 nm node is achievable with significantly reduced target size. Results from dry versus immersion on poly to active
45 nm design rule immersion lithography process layers indicate that a significant reduction in model residuals can be
achieved when HO intrafield overlay models are enabled.
KEYWORDS: Overlay metrology, Metrology, Image segmentation, Front end of line, Semiconducting wafers, Chemical mechanical planarization, Metals, Lithography, Scanning electron microscopy, Scanners
Accurate and precise overlay metrology is a critical requirement in order to achieve high product yield in microelectronic manufacturing. Meeting the tighter overlay measurement error requirements for 90nm technology and beyond is a dramatic challenge for optical metrology techniques using only conventional overlay marks like Bar in Bar (BiB) or Frame in Frames (FiF). New deficiencies, affecting traditional overlay marks, become evident as microlithography processes are developed for each new design rule node. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. In this paper we will review the superior performances of grating-based AIM marks to provide a complete solution to control lithography overlay errors for new generation devices. Examples of successful application of AIM technology to FEOL and Cu-BEOL process steps of advanced non volatile memory devices manufacturing are illustrated. An additional advantage of the adoption of AIM marks is that the significant reduction of target noise versus conventional marks revealed systematic differences within the lithography cluster which were previously obscure offering a new tool to optimize litho cells. In this paper we demonstrated that AIM target architecture enables high performance metrology with design rule segmented targets - a prerequisite to have overlay marks fully compatible with design rule sensitive process steps.
AIM grating targets were optimized and implemented on the metal 2 Aluminum layer in high volume production of 110-nm DRAM devices. Grating target structures are intrinsically more compatible with Aluminum process design rules, allowing overlay target optimization to better fit the process and better cope with the large grain structure of the Aluminum layer. With the implementation of AIM overlay targets we were able to achieve tighter control of the Aluminum patterning, we also achieved smaller overlay residuals, better matching between post litho and post etch measurements, better modeling and less rework. Above all, AIM targets improve the overlay metrology tool capability and provide a better tool-to-tool matching performance.
As Moore's law drives the semiconductor industry to tighter specifications, challenges are becoming real for overlay metrology. A lot of work has been done on the metrology tool capability to improve single-tool precision, tool-to-tool matching and Tool-Induced Shift (TIS) variability. But nowadays these contribute just a small portion of the Overlay Metrology Error (approximately 10% for 90nm technology). Unmodeled systematic, scanner noise and process variation are becoming the major contributors. In order to reduce these effects, new target design was developed in the industry, showing improvements in performance. Precision, Residual analysis, DI/FI (Develop Inspection / Final Inspection) bias and Overlay Mark Fidelity (OMF) are common metrics for measurement quality. When we come to measurement accuracy, we do not have any direct metric to qualify targets.
In the current work we evaluated the accuracy of different AIM (developed by Kla-Tencor) and Frame-In-Frame (FIF) targets by comparing them to reference “SEM” targets. The experiment was conducted using a special designed 65nm D/R reticle, which included various overlay targets. Measurements were done on test wafers with resist on etched poly printed on 248nm scanner.
The results showed that, for this "straight-forward" application, the best accuracy performance was achieved by the Non Segmented (NS) AIM target and was estimated in the order of 1.5 nm site-to-site. This is slightly more accurate than hole-based target and far more than NS FIF target in this particular case. When using the non-accurate NS FIF target, correctable parameters and maximum overlay prediction error analysis, showed up to 24nm overlay error at the edge of the wafer. We also showed that part of this accuracy error can be attributed to the non-uniformity of BARC deposition.
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