Mr. Yoichi Matsuoka Profile

Yoichi Matsuoka

at Canon Inc.

SPIE Involvement:

Author

Publications (9)

Proceedings Article | 23 August 2021 Paper

NIL integration using computational lithography for semiconductor device manufacturing

Tsuyoshi Arai, Sentaro Aihara, Yuichiro Oguchi, Junichi Seki, Yoichi Matsuoka

Proceedings Volume 11908, 119080E (2021) https://doi.org/10.1117/12.2600797

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Computational technologies are still in the course of development for NIL. Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106. Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction (FSI) simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. In this paper, we introduce a new process simulator which directly inputs the process parameters, simulates the whole imprinting process, and evaluates the quality of the resulting resist film. To overcome the scale differences, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region. In addition, the simulator can independently consider the positions of the droplets and calculate the droplet coalescence, thereby predicting the distribution of the non-fill areas which originate from the trapped gas between the droplets. The simulator has been applied to the actual NIL system and some examples of its applications are presented in this work.

Proceedings Article | 22 February 2021 Presentation + Paper

Addressing NIL integration for semiconductor device manufacturing

Sentaro Aihara, Noburu Takakura, Fuma Kizu, Satoru Jimbo, Koji Ishibashi, Junichi Seki, Yuichiro Oguchi, Toshiya Asano, Yoichi Matsuoka, Masahiro Tamura, Osamu Morimoto

Proceedings Volume 11610, 1161007 (2021) https://doi.org/10.1117/12.2584720

KEYWORDS: Nanoimprint lithography, Manufacturing, Computational lithography, Semiconductors, Semiconductor manufacturing, Optical lithography, Semiconducting wafers, Photomasks, Ultraviolet radiation, Physics

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. All lithographic approaches must establish an ecosystem in order to meet the stringent demands for device manufacturing. The table below shows the performance requirements for each category. Throughput is a basic requirement for cost of ownership. Defectivity addresses device yield. Overlay is also needed to enhance device yield. Each device generation places stricter demands on the overlay budget. An infrastructure is required in order to successfully yield advanced devices. In addition, today’s solutions require computational methods and machine learning to meet the requirements described above. The purpose of this paper is to describe the NIL integration requirements, review some of the key solutions for total integration.

Proceedings Article | 12 June 2018 Paper

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography

Tsuyoshi Arai, Yoichi Matsuoka, Hisanobu Azuma

Proceedings Volume 10807, 1080704 (2018) https://doi.org/10.1117/12.2500482

KEYWORDS: Particles, Photomasks, Semiconducting wafers, Nanoimprint lithography, Mask cleaning, Control systems, Semiconductor manufacturing, Liquids, Solids, Photoresist processing

Read Abstract +

Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. The NIL process involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. In this work, methods including in-situ particle removal, mask neutralization and resist filtration are discussed in detail. As a result of these methods, along with already developed techniques, particle counts on a wafer were reduced to only 0.0005 pieces per wafer path or a single particle over 2000 wafers, with a next target of 0.0001 pieces per wafer path. Particle adder reduction correlates directly with mask life, and a mask life of 81 lots (about 2000 wafers) is demonstrated. New methods are now under development to further extend mask and reduce cost of ownership. In this work on-tool wafer inspection and mask cleaning methods are also introduced.

Proceedings Article | 13 July 2017 Paper

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography

Masami Yonekawa, Takahiro Nakayama, Kazuki Nakagawa, Toshihiro Maeda, Yoichi Matsuoka, Keiji Emoto, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10454, 104540R (2017) https://doi.org/10.1117/12.2279365

KEYWORDS: Semiconducting wafers, Curtains, Polishing, Lithography, Liquids, Ceramics, Nanoimprint lithography, Particles, Control systems, Semiconductor manufacturing, Photomasks

Read Abstract +

Proceedings Article | 21 March 2017 Paper

Improved defectivity and particle control for nanoimprint lithography high-volume semiconductor manufacturing

Takahiro Nakayama, Masami Yonekawa, Yoichi Matsuoka, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10144, 1014407 (2017) https://doi.org/10.1117/12.2257647

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Semiconducting wafers, Curtains, Ceramics, Surface finishing, Polishing

Read Abstract +

Proceedings Article | 4 October 2016 Paper

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

Yoichi Matsuoka, Junichi Seki, Takahiro Nakayama, Kazuki Nakagawa, Hisanobu Azuma, Kiyohito Yamamoto, Chiaki Sato, Fumio Sakai, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 9985, 99851G (2016) https://doi.org/10.1117/12.2243114

KEYWORDS: Photomasks, Lithography, Nanoimprint lithography, Semiconducting wafers, Semiconductors, Particles, Semiconductor manufacturing, Curtains, Image resolution, Manufacturing

Read Abstract +

Proceedings Article | 7 March 2008 Paper

Immersion defect performance and particle control method for 45nm mass production

Takahito Chibana, Masamichi Kobayashi, Hitoshi Nakano, Mikio Arakawa, Yoichi Matsuoka, Youji Kawasaki, Masayuki Tanabe, Hirohisa Oda

Proceedings Volume 6924, 69241B (2008) https://doi.org/10.1117/12.774672

KEYWORDS: Semiconducting wafers, Particles, Contamination, Inspection, Scanning probe microscopy, Bridges, Liquids, Water, Deep ultraviolet, Defect inspection

Read Abstract +

Proceedings Article | 26 March 2007 Paper

Contamination and particle control system in immersion exposure tool

Masamichi Kobayashi, Hitoshi Nakano, Mikio Arakawa, Masayuki Tanabe, Koji Toyoda, Takahito Chibana, Yoichi Matsuoka, Youji Kawasaki

Proceedings Volume 6520, 652014 (2007) https://doi.org/10.1117/12.711289

KEYWORDS: Particles, Contamination, Semiconducting wafers, Bridges, Defect inspection, Water, Inspection, Pulsed laser operation, Control systems, Transmittance

Read Abstract +

Proceedings Article | 15 March 2006 Paper

Development status of a 193-nm immersion exposure tool

Takahito Chibana, Hitoshi Nakano, Hideo Hata, Nobuhiro Kodachi, Naoto Sano, Mikio Arakawa, Yoichi Matsuoka, Youji Kawasaki, Sunao Mori, Keiko Chiba

Proceedings Volume 6154, 61541V (2006) https://doi.org/10.1117/12.657010

KEYWORDS: Contamination, Semiconducting wafers, Transmittance, Immersion lithography, Defect inspection, Water, Liquids, Particles, Laser irradiation, Scanners

Read Abstract +

Showing 5 of 9 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years