Edge placement error (EPE) has become a critically important metric in semiconductor manufacturing. EPE quantifies the difference between the designed and printed layout of devices, coupling overlay and critical dimension (CD) of different litho layers. EPE consists of global and local components and can manifest itself between different physical layers of a device (e.g., via, metal) or within a single layer (primarily relevant for multi-patterning). This paper will study the simplest case of a single layer using an N10 litho-etch-litho-etch (LELE) metal layer patterning and will mainly cover global EPE. Monitoring and control of EPE will enable the stability of integrated circuit devices in advanced technology nodes. Inline EPE prediction in the process control loop at previous litho and etch steps enables early wafer status diagnosis and process disposition, which will improve process margin and wafer yield. Overlay and CD are essential inputs for EPE monitoring, prediction and control. Direct measurement of EPE on the device provides a reference value for an EPE model with overlay and CD measured on special targets. KLA’s pattern-centric solutions provide unique and accurate functionality in EPE metrology by analyzing SEM images on devices or targets in combination with the chip design. In this paper, we conduct experiments for EPE modeling and perform reference analysis using KLA’s pattern-centric solutions, targeting a higher pass rate of e-test, lower defectivity and targeted SEM inspection. KLA’s pattern-centric solutions are applied to e-beam images and provide die-to-database analysis by extracting measurements. The resultant EPE analysis can provide a higher correlation between electrical test data and targeted hotspot inspection, and can also be used to build the EPE model, for example, using e-overlay or CD targets. Overall, the results of these studies show good agreement with EPE model predictions and measured EPE by KLA’s pattern-centric solutions on device structures.
In recent years, the pursuit of high storage capacity in 3D-NAND flash devices has driven the addition of more layers to increase the stack height. Challenges arise when etching high aspect ratio memory holes. Due to the existence of a thick and opaque hard mask layer, overlay control faces significant lot-to-lot variation and difficulty of run-to-run feedback control. In this paper, a fundamental study on channel hole overlay variation is revealed by collecting and analyzing step-by step overlay, etch tilt and stress data. The strong correlation between overlay/tilt/stress identifies the main contributor of overlay lot-to-lot variation to be from etch tilt, which also strongly correlates to etch chamber RF hour (accumulated hours the chamber has run since its last PM event) without chamber dependency. In addition, overlay simulations showed lots grouped by RF hour can effectively reduce lot-to-lot overlay variation.
Self-aligned quadruple patterning (SAQP) has quickly become the most viable multi-patterning scheme adopted for manufacturing critical layers in logic and memory devices below the 10nm (N10) technology node. Occurrence of pitch walk is a very common phenomenon in post SAQP layers. If not properly managed, the absolute value and variability of pitch walk could result in either parametric yield degradation or catastrophic fin-loss defects. These issues result from the interaction with subsequent processes, such as keeps and cuts, which are used to define and isolate fin groups for building the transistors. Previous studies have shown that a combined lithography and etch methodology would help reduce the pitch walk impact [1]. In this article, we will show advanced control for SAQP pitch walk using a combined scheme of lithography, deposition and etch actuators, in a front end 5nm logic process. By the implementation of a rigorous pitch walk prediction model that is calibrated and validated with wafer data, we then expand the model coverage to include an edge placement error component. This accounts for the contribution of overlay from subsequent layers to predict patterning defect probability at the final stage of device structure formation. With this approach, we can identify the optimal process control loop that minimizes pitch walk effects while maximizes the process margin for subsequent layers for this integration scheme.
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