Die-to-database inspection of optical patterned masks enables defect detection and subsequent repair for creation of defect-free masks regardless of single- or multi-die layout. The components required for optical die-to-database inspection include (1) optical photomask inspection tool with sufficient resolution to resolve the patterns of interest, (2) computational resources for (a) preparation of mask pattern data + (b) algorithms for detection and noise reduction to distinguish real defects from background variation, and (3) network and storage infrastructure to tie it all together. In this paper, we will present the first implementation of the die-to-database inspection flow on the MATRICS tool. To maximize tool utility, the system architecture decouples tool and compute resources, such that non-die-to-database inspections can proceed while die-to-database inspection also remains underway. Details of the mask pattern data preparation will be presented alongside real examples of detection capability from an Intel mask shop.
As the semiconductor industry advances to ever-smaller nodes with finer feature sizes and more complex mask designs, reticle quality and reticle defects continue to be a top mask yield risk. The primary reticle defect quality requirement is defined as “no reticle defects causing 10% or larger CD error on wafer”. Beginning at around the 7 nm Logic node, EUV lithography will start pilot production in several leading fabs. EUV masks stress reticle defectivity requirements for mask shops even more than optical masks due to the larger printing impact from a similar size defect on the mask, and the greater cost and longer cycle time for EUV masks. In a mask shop, generally there are three use cases for a blank inspection system, which are used to monitor and improve mask defectivity; 1) Inspecting process monitor masks, which are used to partition the mask process and identify defect excursions, 2) inspecting ‘witness’ blanks, which are used to measure and control defectivity in each process tool / chamber and 3) inspecting incoming mask blanks to ensure defect-free starting materials for advanced optical and EUV reticles. Traditionally, mask shops have been using bright field confocal technology to perform these tasks. However, due to more stringent defect requirements and the flexibility necessary to support these varied use cases, the industry requires a new approach to drive yield improvements in mask manufacturing. In this paper, we report on the introduction of a new system that provides superior sensitivity, with very high throughput and the flexibility to adapt to many different use cases in a production environment.
Classification and Printability of EUV Mask Defects from SEM images EUV lithography is starting to show more promise for patterning some critical layers at 5nm technology node and beyond. However, there still are many key technical obstacles to overcome before bringing EUV Lithography into high volume manufacturing (HVM). One of the greatest obstacles is manufacturing defect-free masks. For pattern defect inspections in the mask-shop, cutting-edge 193nm optical inspection tools have been used so far due to lacking any e-beam mask inspection (EBMI) or EUV actinic pattern inspection (API) tools. The main issue with current 193nm inspection tools is the limited resolution for mask dimensions targeted for EUV patterning. The theoretical resolution limit for 193nm mask inspection tools is about 60nm HP on masks, which means that main feature sizes on EUV masks will be well beyond the practical resolution of 193nm inspection tools. Nevertheless, 193nm inspection tools with various illumination conditions that maximize defect sensitivity and/or main-pattern modulation are being explored for initial EUV defect detection. Due to the generally low signal-to-noise in the 193nm inspection imaging at EUV patterning dimensions, these inspections often result in hundreds and thousands of defects which then need to be accurately reviewed and dispositioned. Manually reviewing each defect is difficult due to poor resolution. In addition, the lack of a reliable aerial dispositioning system makes it very challenging to disposition for printability. In this paper, we present the use of SEM images of EUV masks for higher resolution review and disposition of defects. In this approach, most of the defects detected by the 193nm inspection tools are first imaged on a mask SEM tool. These images together with the corresponding post-OPC design clips are provided to KLA-Tencor’s Reticle Decision Center (RDC) platform which provides ADC (Automated Defect Classification) and S2A (SEM-to-Aerial printability) analysis of every defect. First, a defect-free or reference mask SEM is rendered from the post-OPC design, and the defective signature is detected from the defect-reference difference image. These signatures help assess the true nature of the defect as evident in e-beam imaging; for example, excess or missing absorber, line-edge roughness, contamination, etc. Next, defect and reference contours are extracted from the grayscale SEM images and fed into the simulation engine with an EUV scanner model to generate corresponding EUV defect and reference aerial images. These are then analyzed for printability and dispositioned using an Aerial Image Analyzer (AIA) application to automatically measure and determine the amount of CD errors. Thus by integrating EUV ADC and S2A applications together, every defect detection is characterized for its type and printability which is essential for not only determining which defects to repair, but also in monitoring the performance of EUV mask process tools. The accuracy of the S2A print modeling has been verified with other commercially-available simulators, and will also be verified with actual wafer print results. With EUV lithography progressing towards volume manufacturing at 5nm technology, and the likelihood of EBMI inspectors approaching the horizon, the EUV ADC-S2A system will continue serving an essential role of dispositioning defects off e-beam imaging.
As Moore’s Law continues its relentless march toward ever smaller geometries on wafer, lithographers who
had been relying on the implementation of a solution using EUV lithography are faced with increasing
challenges to meet requirements for printing sub-2x nm half-pitch (HP). The available choices rely on 193 nm DUV immersion lithography, but with decreasing k1 values and thus shrinking process windows. To overcome these limitations, two techniques such as inverse lithography technology (ILT) and source mask optimization (SMO) were introduced by computational OPC scheme.
From a mask inspection viewpoint, the impact of both ILT and SMO is similar – both result in photomasks that have a large quantity of sub-resolution assist features (SRAFs). These SRAFs are challenging for mask-makers
to pattern with high fidelity and accuracy across a full-field mask, and thus mask inspection is challenged to maintain a high sensitivity level on primary mask features while not suffering from a high nuisance detection rate on the SRAF features. To solve this particular issue, new inspection approach was developed by using computational image calibration based wafer scanner simulation. This paper will be described the new
capabilities, which analyzes the aerial image to differentiate between printing and non-printing features, and
applying the appropriate sensitivity threshold. All analysis will be shown comparing results with and without the
new capabilities, with an emphasis on inspectability improvements and nuisance defect reduction to improve
mask cycle time.
As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks
becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical
techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate
the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view
(FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics.
For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a
long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of
masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement
sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns
are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the
mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a
statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in
order to maximize the coverage area on a mask.
In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data
base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the
patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle
multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its
fundamental performance such as accuracy, repeatability, and correlation with other CD metrology tools with a set of
logic masks.
We report inspection results of EUVL masks with 193nm wavelength tools for 30nm and 24nm half-pitch nodes. The
dense line and space and contact pattern is considered to study inspection capability. The evaluation includes defect
contrast variation depending on illumination conditions, defect types, and design nodes. We show many inspection
images with various optic conditions. Consequently, the detection sensitivity is affected by contrast variation of defects.
The detection sensitivity and wafer printability are addressed with a programmed defect mask and a production mask.
With these results, we want to discuss the capability of current EUVL mask inspection tools and the future direction.
Extreme Ultra Violet Lithography (EUVL) is one of the most advanced patterning technologies to overcome the critical
resolution limits of current ArF lithography for 30nm generation node and beyond. Since EUVL mask manufacturing
process has not been fully stabilized yet, it is still suffering from many defect issues such as blank defects, defects inside
multilayer causing phase defects, CD defects, LERs (Line Edge Roughness), and so on. One of the most important
roles in mask manufacturing process belongs to mask inspection tools, which monitor and visualize mask features,
defects and process quality for the EUVL process development. Moreover, as the portion of EUV mask production has
been increased due to the EUV Pre-Production Tool (PPT) development, mask inspection technologies for EUVL
become highly urgent and critical to guarantee mask quality. This paper presents a promising inspection technique for
increasing the contrast of pattern imaging and defects capture rate using configurable illumination conditions in 193nm
wavelength inspection tool.
As the design rule of wafer has been shrinking, the patterns on the mask also need to be getting smaller and even
smaller for some sub-resolution assist features, which makes mask inspection process need a high resolution (HR)
inspection systems. For this HR mask inspection, most mask inspector makers adopt a TDI(Time Delay & Integration)
sensor to enhance acquired image quality with the acceptable scan speed, thus, to minimize the inspection cost.
However, even TDI sensor may not get a sufficient gray level of pattern image for the most advanced mask patterns.
Furthermore, it might generate some false defects depending on the pattern shape and scan direction (in combination
with pattern direction). We manufactured two programmed defect masks (PDM); one is a ArF EPSM and another is a
EUV mask. By inspecting these masks with perpendicular scan directions, respectively, we evaluated the correlation
between scan direction and defect size/shape experimentally. We found that the inspection with the parallel direction to
pattern direction can increase the inspectability for the patterns and the defect sensitivity since this helps to enhance
signal to noise ratio from the TDI sensor. Our analysis can increase sensitivity of TDI sensor effectively without any
additional hardware modification.
OPC (Optical Proximity Correction) technique is inevitable and getting more complex to resolve finer features on
wafer with existing optical lithography technology. Some SRAFs generated with special model-based OPC engines
are so sophisticated that we can hardly imagine final patterns on wafer simply by seeing patterns on reticle. These
model-based OPCs consist of many kinds of assist features since they are designed differently according to various
target features on wafer and lithographic conditions. Not only small main features but also even smaller and
aggressive SRAFs (Sub Resolution Assist Features) may cause too many false counts and/or nuisance defects during the
reticle inspection, which makes inspection TAT (Turn Around Time) longer and inspection process more laborconsuming.
To improve the inspectability of this sort of complex OPC patterns, appropriate MRC (Mask Rule Check)
rules should be considered.[1][2] As far as the inspection methods are concerned, several approaches have been
developed, such as TLD (Thin Line Desense), LPI (Lithographic Plane Inspection)[3][4], and Aerial Image Based
Inspection[5][6] to relax MRC rules. In this paper, we've compared and analyzed the functionalities of enhanced
inspection methods for complex OPC features of 4x nodes and beyond.
As the design rule shrinks continuously, a reticle inspection is getting harsh and harsh and is now one of the most
critical issues in the mask fabrication process. The reticle inspection process burdens the entire mask process with the
inspectability and detectability problems. Not only aggressive assist features but also small and dense main features
themselves may cause many false detection alarms or nuisance defects, which makes the inspection TAT (Turn-around
Time) longer. Moreover, small and dense patterns inspections always come with the defect detectability issues.
Detectability of a defect in small and dense patterns is usually inferior to the printability of it because of the high MEEF
(Mask Error Enhancement Factor) resulted by those small and dense patterns.
Double Patterning Technology (DPT)[1] can relief the pattern pitch effectively, therefore, DPT reticle pattern can
have a larger pitch than normal Single Patterning Technology (SPT) reticle. We investigate the effect of this pitch
relaxation of DPT reticle on the inspection process.
In this paper, we compare and analyze the difference of pattern inspectability and defect detectability between DPT
reticles and SPT reticles when they have same size of patterns on them. In addition to these results, we also
investigate the printability of defects in comparison with the detectability and derive the requirement of the inspection
for 4x nodes DPT reticles from the results.
One of the major topics for the introduction of extreme ultraviolet (EUV) technology is the availability of defect-free
masks. From the mask makers' perspective, the quality of the incoming blank material is one of the key ingredients
impacting the yield of structured masks. Besides flatness and layer thickness uniformity, the number of defects
determines the final quality of the mask delivered to the customer for printing. Defects within the layers of optical blanks
have shown that they have a growing impact on the mask structuring process, well below the usual defect specifications
of the blanks. It is expected that this finding will also hold true for material layers above the multi-layer. In addition to
printing performance, EUV masks need to have a defect-free multi-layer. While this layer is easily accessible during
blank production, mask makers usually acquire the complete blank stacks with or without the coated resist. Incoming
blank inspection, therefore, must check the quality of the complete stack without destroying any of the functionality of
these layers. Siemens and AMTC have jointly developed a blank inspection tool that has been installed in AMTC's
Dresden facility and that allows the screening of an EUV blank under these boundary conditions. Previously,
SEMATECH successfully installed an M7360 from Lasertec in its Mask Blank Development Center (MBDC) in Albany,
NY, that shows much better sensitivity data than SEMATECH's earlier tool, the Lasertec M1350. This paper describes
the early performance of the Siemens DF-40XP on programmed multi-layer defect blanks and regular blanks and
compares it to that of the existing tools at the SEMATECH MBDC.
Determining the printability of substrate defects beneath the extreme ultraviolet (EUV) reflecting multilayer stack is an
important issue in EUVL lithography. Several simulation studies have been performed in the past to determine the
tolerable defect size on EUV mask blank substrates but the industry still has no exact specification based on real
printability tests. Therefore, it is imperative to experimentally determine the printability of small defects on a mask
blanks that are caused by substrate defects using direct printing of programmed substrate defect in an EUV exposure
tool.
SEMATECH fabricated bump type program defect masks using standard electron beam lithography and performed
printing tests with the masks using an EUV exposure tool. Defect images were also captured using SEMATECH's
Berkeley Actinic Imaging Tool in order to compare aerial defect images with secondary electron microscope images
from exposed wafers.
In this paper, a comprehensive understanding of substrate defect printability will be presented and printability
specifications of EUV mask substrate defects will be discussed.
The readiness of a defect-free extreme ultraviolet lithography (EUVL) mask blank infrastructure is one of the main
enablers for the insertion of EUVL technology into production. It is essential to have sufficient defect detection
capability and understanding of defect printability to develop a defect-free EUVL mask blank infrastructure. The
SEMATECH Mask Blank Development Center (MBDC) has been developing EUVL mask blanks with low defect
densities with the Lasertec M1350 and M7360, the 1st and 2nd generations, respectively, of visible light EUVL mask
blank inspection tools. Although the M7360 represents a significant improvement in our defect detection capability, it
is time to start developing a 3rd generation tool for EUVL mask blank inspection. The goal of this tool is to detect all
printable defects; therefore, understanding defect printability criteria is critical to this tool development.
In this paper, we will investigate the defect detectability of a 2nd generation blank inspection tool and a patterned
EUVL mask inspection tool. We will also compare the ability of the inspection tools to detect programmed defects
whose printability has been estimated from wafer printing results and actinic aerial images results.
The capability of SEMATECH's Lasertec M7360 inspection tool to detect particles of different sizes and composition was studied on the surface of fused silica and MoSi multilayers (MLs) with a Si cap layer. Particles of Au, Ag, SnO2, Fe2O3, and Al2O3 were deposited and inspected 10 times with the M7360. Tool pixel size histograms were used to calculate the average pixel size per particle category. The calibration curves of pixel size for polystyrene latex (PSL) spheres were used to convert the average pixel size to the optical size of the defects as detected by the M7360. Selective sets of each category of particles then were reviewed by atomic force microscope (AFM) to calculate the sphere equivalent volume diameter (SEVD) of the particles. The contribution of the surface on which particles were deposited and defect composition and shape were studied. Our results indicate that for Fe2 O3 and SnO particles, size distribution on the surface of fused silica and MLs is similar and no effect of the substrate was observed. The AFM-measured SEVD size of particles were close to the nominal size of particles specified by the particle supplier. Optical size of particles were found to be larger or smaller than SEVD size for the different particles. In the case of the Au particles, the PSL equivalent optical size was found to be larger than the SEVD in good agreement with the modeling. By using prefabricated rectangular defects on a fused silica surface, we showed that the M7360 differentiates between the PSL and SEVD size of prefabricated defects. The PSL size is smaller than the SEVD size of prefabricated defects for particle sizes below 100 nm.
The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography
(EUVL) into manufacturing. Evidently, the success of the industry's mask blank defect reduction effort will critically
depend on the timely availability of defect inspection tools that can find ever smaller defects. The first generation of
defect inspection tools enabled SEMATECH's Mask Blank Development Center (MBDC) to reduce mask blank defects
to a level sufficient for use in EUV alpha tools. The second tool generation is currently enabling the MBDC to meet
EUV pilot line requirements by the end of 2007. However, to meet high volume manufacturing (HVM) mask blank
defect requirements for 32 nm half-pitch (hp) patterning, the industry needs a third generation of defect inspection tools.
This next EUV inspection tool generation must be able to find defects of ≤ 20 nm on mask blanks with a high capture
rate and high blank throughput. In addition, these tools will also need to support extendibility assessments of low defect
deposition technologies and the associated infrastructure towards meeting 22 nm half-pitch defect specifications. While
visible light inspection is likely to support defect inspection needs for mask substrates over several technology nodes,
the industry must explore other options for mask blanks and patterned masks. Evaluating the use of inexpensive printing
tools and wafer-based inspection to search for repeating defects must be part of an overall strategy to address mask
blank and patterned mask defect inspection.
Excellent progress has been made over the past years in meeting the demanding specifications for commercial extreme
ultraviolet (EUV) mask blanks. But as EUV technology is being prepared for pilot-line introduction later this decade, a
substantial effort is still required in many EUV mask infrastructure areas. These include defect inspection, reticlehandling
standardization, substrate and mask flatness, and resulting overall mask cost of ownership (CoO). Defect
inspection metrology for finding printable defects of < 30 nm polystyrene latex (PSL) size is a key EUV mask
infrastructure enabler. To meet EUV mask blank production specifications for 32 nm half-pitch (hp) manufacturing, a
next generation EUV mask blank inspection technology will be needed in 2-3 years. The industry must soon adopt
standards for EUV reticle handling including carrier and loadport solutions for unified requirements to support
commercial pilot-line and production tool developments. The stringent mask substrate flatness specification will be very
difficult to meet and is likely to significantly increase overall EUV mask cost. The industry needs to correct for nonflatness
at the various stages of a mask life cycle and must develop respective standards and specifications to determine
what kind of non-flatness can be corrected. For EUV lithography to be successful, it must be affordable. Lower EUV
mask costs have been a key advantage for EUV compared to optical mask extensions. To maintain this advantage, mask
manufacturing and metrology methods while supporting aggressive mask specifications must remain cost competitive.
Extreme ultraviolet lithography (EUVL) mask blanks must be free of printable defects. The SEMATECH Mask Blank
Development Center (MBDC) is focused on driving down the defect density of EUVL mask blanks by providing a
collaborative environment for EUVL mask substrate and equipment suppliers and a state-of-the-art analytical toolset for
them to improve their products. Multilayer (ML) coating, substrate cleaning, and substrate suppliers are on site
improving their products with a toolset that includes defect inspection, multilayer deposition, and substrate cleaning
capabilities. X-ray diffraction (XRD) and EUV reflectance measurement capability as well as focused ion beam
scanning electron microscopy/energy-dispersive X-ray (FIBSEM/EDX) and atomic force microscopy (AFM) for defect
characterization are on site.
The SEMATECH MBDC has just installed a Lasertec M7360, an advanced EUV mask blank inspection tool. The
M7360 operates at a much shorter wavelength than the previous generation of confocal scanning inspection tools
(266nm vs. 488nm for the M1350). The M7360 represents a significant improvement in our defect detection
sensitivity. This paper will center on the capabilities of this new tool and show initial inspection results on EUV
multilayer at sensitivities well below those that have been previously reported.
RET (Resolution Enhancement Technique) is strongly required for 65nm node pattern generation. Alternating Phase Shift Masks (APSM) and Chrome-less Phase Lithography (CPL) masks are widely used for the purpose of RET. However, APSM and CPL mask manufacturing is rather complex and difficult in terms of their structure and fabrication. To inspect these kind of RET masks is very difficult because of quartz (Qz) phase defects which can hardly be detected by using a conventional inspection method. Since Qz phase defect is the key issue in APSM or CPL mask manufacturing, many works have been done widely so far. Here we've evaluated the defocus inspection method to find best inspection condition for detecting Qz phase defects. We conclude that the best condition for finding Qz phase defects could have dependency upon the pattern shape and size. Moreover, the limitation of the inspection capability for Qz phase defect inspection has been addressed with comparison of the wafer print result.
As the design rule continues to shrink towards 65nm size and beyond the defect criteria are becoming ever more challenging. Pattern fidelity and reticle defects that were once considered as insignificant or nuisance are now becoming significant yield impacting defects. The intent of this study is to utilize the new generation DUV system to compare Die-to-Die Reflected Light inspection and Die-to-Die Transmitted Light Inspection to increase defect detection for optimization of the 65nm node process.
In addition, the ReviewSmart will be implemented to help categorically identify systematic tool and process variations and thus allowing user to expedite the learning process to develop a production worthy 65nm node mask process. The learning will be applied to Samsung's pattern inspection strategy, complementing Transmitted Light Inspection, on critical layers of 65 nm node to gain ability to find defects that adversely affect process window.
Defect is a killing factor in photomask fabrications. For 65nm node photomask fabrication, even smaller than 1 um particle can cause hard-to-repair defect. And it is not easy to find the defect source and solve it. For this reason, the process monitoring system that shows us current defect trend rapidly and effectively is highly required. At the same time, this system can be used for verifying the process stability and detecting unusual signals in process.
As the design rule of lithography becomes smaller, printability of reticle defect to wafer is critical for the photomask manufacturing technology. In order to improve the controllability of reticle defects, inspection and repair systems are expanding their capability by continuously modifying hardware and software. This is a good solution to detect and review the defect but it is indirect approaching to reduce the defect in the photomask process. To produce the photomask of defect free or low defect density, effort is needed to improve the capability of defect control in the mask-making process and to evaluate the source of hard defect as well as soft defect. In this paper, we concern the defect source and the feature of printed defects in photomask manufacturing steps. We also discuss the efforts to eliminate the defect source and to control the mask-making process with low defect density. In order to eliminate the source of defects, we partition the mask-making process with defect inspection system, SLF27 TeraStar and Lasertec MD2000, and review a defect shape with CD SEM and AFM. And we compare printed defects, which exist in each process steps, after dry etching process.
As the design rule of lithography becomes smaller, printability of reticle defect to wafer is crucial for the photomask manufacturing technology. In order to improve the controllability of reticle defects, inspection and repair systems are expanding their capability by continuously modifying hardware and software. This is a good solution to detect and review the defect but it is indirect approaching to reduce the defect in the photomask process. To produce the photomask of defect free or low defect density, effort is needed to improve the capability of defect control in the mask-making process and to evaluate the source of hard defect as well as soft defect.
In this paper, we concern the defect source and the feature of printed defects in photomask manufacturing steps. We also discuss the efforts to eliminate the defect source and to control the mask-making process with low defect density. In order to eliminate the source of defects, we partition the mask-making process with defect inspection system, SLF27 TeraStar and Lasertec MD2000, and review a defect shape with CD SEM and AFM. And we compare printed defects, which exist in each process steps, after dry etching process.
As the design rule of semiconductor devices shrinks dramatically, the reticle defect detectability and its specification need to be more tighten than before. Moreover, the fact that most of critical layer from DRAM mass productions are processed with using PSM gives us high defect printability, which burdens the reticle inspection processes. To analyze the specification of PSM defect, the programmed defect test plate was designed and fabricated. The programmed defect test reticle contains some critical DRAM patterns with different design rules (150 nm to 110 nm node) for the low k1 KrF lithography. Various kinds of defect were programmed in the test reticle. After inspection of this test plate and wafer exposure, the results of detectability and those of printability were compared and the defect printability dependency on design rule and wafer illumination conditions was analyzed. Finally the PSM defect specification is derived from these results for sub 130 nm KrF lithography.
Assist features are recently employed in high density devices. But the application seems to be burdening to mask manufacturers. In this paper, considerations for making masks bearing assist features are discussed. A mask grid size, minimum resolution, CD linearity, pattern fidelity, and mask inspectability are among those considerations. For a 0.13 micrometer node, the grid size <EQ 5 nm (4X) is recommended according to our simulation. A high acceleration voltage (50 keV) e-beam writer is found to be a good tool for 0.26 micrometer (4X) assist features necessary for 0.13 micrometer node. A currently available inspection machine should give a good potential to detect defects on a 0.18 micrometer (4X) assist feature bearing mask.
Delay effects were evaluated for various chemically amplified resist (CAR) types in view of exposure conditions, vacuum and atmosphere. Since the mask is exposed in the vacuum chamber for a long period of time, unexpected phenomenon has been emerging in CAR such as pattern degradation, line width variation owing to vacuum delay effect (VDE). In the acetal resist based on ethyl vinyl ether (EVE), the VDE emerges as space CD decrease, while post exposure delay (PED) in an optical process shows space CD increase. Acrylate resist and modified acetal resist are superior in VDE as well as PED to EVE resist. VDE seems to be caused by out-gassing. It can be overcome by choosing out-gassing free chemistry such as acrylate and modified acetal. An over-coating method was evaluated to prevent any volatile materials in CAR from being evaporated in the vacuum, but it is disclosed ineffective to VDE. CAR linearity reaches to 0.2micrometers , and its resist and Cr pattern as well as OPC was equivalent to current e-beam resist, ZEP7000. Finally, we can have achieve 8.3nm CD non- uniformity in 3(sigma) in 135*135 mm2 area that allows beyond 0.13micrometers device mask application.
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