KEYWORDS: Optical lithography, Lithography, Double patterning technology, Photomasks, Very large scale integration, Process control, Manufacturing, Manufacturing equipment, Integrated circuits, Integrated optics, Current controlled current source
Triple patterning (TP) lithography becomes a feasible technology for manufacturing as the feature size further scale down to sub 14/10 nm. In TP, a layout is decomposed into three masks followed with exposures and etches/freezing processes respectively. Previous works mostly focus on layout decomposition with minimal conflicts and stitches simultaneously. However, since any existence of native conflict will result in layout re-design/modification and reperforming the time-consuming decomposition, the effective method that can be aware of native conflicts (NCs) in layout is desirable. In this paper, a bin-based library matching method is proposed for NCs detection and layout decomposition. First, a layout is divided into bins and the corresponding conflict graph in each bin is constructed. Then, we match the conflict graph in a prebuilt colored library, and as a result the NCs can be located and highlighted quickly.
Robust inverse mask synthesis is computationally intensive, and its turnaround time continues to rise hand-in-hand with the ever-shrinking integrated circuit feature size. We report the development of a cascadic multigrid (CMG) algorithm for robust inverse mask synthesis, which starts from a relatively coarse mask grid and refines it iteratively in stages, so as to achieve significant speedup without compromising numerical accuracy. Since the CMG algorithm entails frequent changes of the computational grid size, we need to intentionally introduce an analytical circle-sampling technique for modeling the forward lithography imaging and employ an edge distance error as metric to guide mask synthesis. These two techniques work nicely with variable grid sizes and are well suited for our CMG algorithm. As a result, our algorithm achieves more than four times speedup over conventional methods that synthesize a mask on a fixed fine grid. Numerical results are presented to demonstrate the validity and efficiency of the proposed method.
As critical dimension shrinks, pattern density of integrated circuits gets much denser and lithographic process variations become more pronounced. In order to synthesize masks that are robust to process variations, the average wafer performance with respect to process fluctuations is optimized. This approach takes into account process variations explicitly. However, it needs to calculate a large number of optical images under different process variations during its optimizing process and thus significantly increases the computational burden. Most recently, we proposed a convolutionvariation separation (CVS) method for modeling of optical lithography, which separates process variables from the coordinate system and hence enables fast computation of optical images through a wide range of process variations. In this work, we detail the formulation of robust inverse lithography making use of the CVS method, and further investigate the impacts of arbitrary statistical distribution of process variations on the synthesized mask patterns.
We propose a new regularization framework for inverse lithography that regularizes masks directly by applying a mask filtering technique to improve computational efficiency and to enhance mask manufacturability. This technique is different from the conventional regularization method that regularizes a mask by incorporating various penalty functions to the cost function. We design a specific mask filter for this purpose. Moreover, we introduce a metric called edge distance error (EDE) to guide mask synthesis and establish the correlation between pattern error and edge placement error (EPE) via EDE. We prove that EDE has the same dimension as EPE and has a continuous expression as pattern error. Simulation results demonstrating the validity and efficiency of the proposed method are presented.
In this paper, we propose a new regularization framework that regularizes mask directly by applying a mask filtering technique to improve computational efficiency and enhance mask manufacturability for pixel-based Inverse Lithography Technique (ILT). Generally, the synthesized mask by pixel-based ILT is a grey-level image, and possesses small, unwanted block objects, such as isolated holes, protrusions, and jagged edges, which are unreachable in the real manufacturing process. The proposed method filters (or regularizes) mask directly to guarantee manufacturability of the synthesized mask pattern; this technique is different from the conventional regularization method that regularizes mask by incorporating various penalty functions to a cost function. A tailored mask filter is developed in this special ILT case. In addition, we introduce a new metric, edge distance error which has the same dimension nanometer as edge placement error and has a continuous expression as pattern error, to guide mask synthesis. Simulation results demonstrating the validity and efficiency of the proposed method are presented.
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