Advanced IC fabs must inspect critical reticles on a frequent basis to ensure high wafer yields. These necessary requalification inspections have traditionally carried high risk and expense. Manually reviewing sometimes hundreds of potentially yield-limiting detections is a very high-risk activity due to the likelihood of human error; the worst of which is the accidental passing of a real, yield-limiting defect. Painfully high cost is incurred as a result, but high cost is also realized on a daily basis while reticles are being manually classified on inspection tools since these tools often remain in a non-productive state during classification. An automatic defect analysis system (ADAS) has been implemented at a 20nm node wafer fab to automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this paper, we have studied and present results showing the positive impact that an automated reticle defect classification system has on the reticle requalification process; specifically to defect classification speed and accuracy. To verify accuracy, detected defects of interest were analyzed with lithographic simulation software and compared to the results of both AIMS™ optical simulation and to actual wafer prints.
Chromeless PSM photomasks have been successfully applied to a production memory application. This 248-nm application has allowed an extremely aggressive, dense design to be successfully deployed without changing wavelength. This was achieved with an advanced resolution enhancement technique, a chromeless phase-shifting mask, to provide a more cost-effective total lithographic solution. The key to this technology is a mask that delivers high wafer-die yields, while delivering resolution at low k1. Therefore, the mask must have zero printing defects. In order to understand printing defects, many types of potential defects were analyzed and correlated back to the mask locations using both a 248-nm AIMs tool and SEM images. These defects were also correlated to a 257-nm KLA 576 tool using die-to-die inspection runs. This paper will examine chromeless mask phase-defect printing effects by using inspection capture at the key manufacturing steps (post-Cr etch, post-Qz Etch, and post-Cr removal). These defects will then be tracked through processes using SEM, AIMs, RAVE repair, and post-repair AIMs.
Increasing numbers of MEMS, photonic, and integrated circuit manufacturers are investigating the use of Nano-imprint Lithography or Step and Flash Imprint Lithography (SFIL) as a lithography choice for making various devices and products. Their main interests in using these technologies are the lack of aberrations inherent in traditional optical reduction lithography, and the relative low cost of imprint tools. Since imprint templates are at 1X scale, the small sizes of these structures have necessitated the use of high-resolution 50KeV, and 100KeV e-beam lithography tools to build these templates. For MEMS and photonic applications, the structures desired are often circles, arches, and other non-orthogonal shapes.
It has long been known that both 50keV, and especially 100keV e-beam lithography tools are extremely accurate, and can produce very high resolution structures, but the trade off is long write times. The main drivers in write time are shot count and stage travel. This work will show how circles and other non-orthogonal shapes can be produced with a 50KeV Variable Shaped Beam (VSB) e-beam lithography system using unique pattern transforms and primitive shapes, while keeping the shot count and write times under control. The quality of shapes replicated into the resist on wafer using an SFIL tool will also be presented.
At SPIE Microlithography 2005, the concept of direct imprinting of dielectric material for dual damascene processing and its benefits was introduced 1. Manufacturing a nano-imprint template with multi-tier 3-D structures presents a unique set of challenges. The main issues are patterning two different mask layers with good overlay and etch depth control into the quartz at each step on the same substrate. This work describes the tools and processes used to build these types of structures in a commercial photomask shop. The results of using a template with two levels of patterning to imprint dual damascene 3-D structures will also be presented.
A novel approach to improve the imaging of the critical magnetic pole structure in the disk drive read head is introduced. A 90-degree sub-resolution opening is added to an alternating aperture phase shift mask to reduce a strong proximity effect in the non-Manhattan tapered section, while maintaining the enhanced printability of the linear segment of the pole region.. Simulation indicates that this opening provides a method to correct the observed distortion in the printed edge without reducing the effectiveness of the altPSM character of the pole itself. We have designed test patterns with this concept and built photomasks to evaluate mask manufacturability and to empirically test the impact of the 90-degree window on final pattern fidelity on wafer. Preliminary results indicate positive correction effects, as well as some potential issues which may be resolved using additional, established correction approaches.
CPL and aerial image mapping type contact designs for both negative and positive tones were created, built and tested for 100 nm and sub-100 nm contacts. Experimental results illustrated the need for electromagnetic-field corrections in the simulations. Resolution down to 80nm dense contacts were seen with both negative and positive resists with acceptable process windows though some process optimization is still required as unacceptable CD variation and a reentrant profile was observed. High MEEF requires strict CD control on the mask. Data volume for the isolated contact designs can also challenge the mask build.
Lithography costs for IC production at resolutions of 65-nm and beyond have grown exponentially for each technology node and show no sign of slowing. Step and Flash Imprint Lithography (S-FIL), developed at the University of Texas (UT) uniquely offers IC manufacturers the potential for lower cost of ownership, because S-FIL does not require expensive optics, advanced illumination sources or chemically amplified resists (CAR). The SIA’s addition of Imprint Lithography to the International Technology Roadmap for Semiconductors (ITRS) in 2003, indicates the promise to become a preferred technology and has some compelling advantages over traditional 4X optical lithography.
Advanced 90nm binary & phase shift mask processes have been altered using thin Cr (15-nm) & thin e-beam resist (<150nm) resulting in sub 100-nm geometries necessary for S-FIL, and have become the baseline for template manufacture. Commercial production of advanced 1X templates requires CD metrology capability beyond the equipment typically used in 4X mask making. Full commercialization of Imprint Lithography requires not only the ability to generate a 1X template but also a metrology solution that can characterize critical dimension (CD) parameters of the template. Previous published work on S-FIL has focused mainly on high resolution templates produced on 100keV Gaussian pattern generators (PG), and has shown that resolution is only limited by the template.
This work demonstrates that an advanced commercial photomask facility can fabricate templates with sub-100 nm critical dimensions, and that the CDs can be characterized using a commercially available CD-SEM metrology tool. CD metrology repeatability of 0.7nm 3σ was established on a quartz only template with a 6025 form factor.
As the semiconductor-process technology advances towards the 90nm-node, more and more wafer-fabs start to use 193nm EAPSM (Embedded Attenuated Phase-Shift Mask) technology as the main lithography strategy for the most critical-layers. Because the 193nm EAPSM is a relative new technology in the semiconductor industry, it is important for us to understand the key-mask-specifications in a 193nm EAPSM and their impact to the wafer process windows. In this paper, we studied the effects of phase-angle and transmission to the wafer process window of a 193nm-EAPSM in a 300mm wafer-manufacturing environment. We first fabricated a special multi-phase EAPSM by a combination of extra Quartz-etch and Mosi-removal. We then used a high NA 193nm scanner (ASML-ALTA1100) and high contrast resist to perform the wafer-level printing study. To fully understand the impact of phase-angle and transmission to wafer process windows, we also used AIMS (Aerial-Image Measurement System) and Prolith simulation software to study the lithographic performances of various phase-angle and transmission combinations. By combining the wafer-level resist imaging printing results, AIMS studies and Prolith-2 lithography simulations, we proposed the practical phase-angle and transmission specifications for the 90nm-node wafer process.
AAPSM masks require OPC correction through pitch in order to print a linear dark line response vs the design CDs. The masks also require correction for the clear intensity imbalance caused by the phased etched Qz wall edge. The clear intensity can be balanced by two approaches;(or a combination of the two) data biasing or wet undercut etching of the Qz etched opening. IC manufacturers would like to use one OPC model that will work for any mask fabrication approach. This paper shows that there is no OPC difference observed in either the aerial image or the printed image of several OPC learning patterns. The study includes CD through pitch for dense (1:1) L/S Patterns and Isolated Line CD vs line-space ratio. The images were analyzed for the dark line linearity, the clear CD balance though pitch, and the clear CD balance with focus (phase error effects -PES).
Reticle costs are increasing as users tighten specifications to accommodate the shrinking process windows in advanced semiconductor lithography. Tighter specs often drive the use of e-beam based mask processes, which produce better mask pattern acuity than laser-based tools but suffer lower throughput (and thus higher costs). In some cases, such as contacts, the pattern acuity of an e-beam tool does not seem to be required -- but the tight effective CD uniformity typically produced by an e-beam mask writer is still necessary to prevent wafer level defect problems. This presents problems for the maskshop (e.g., low yield and long cycle time) as well as for the fab (more expensive new product introduction, uncertainty in mask delivery). This paper describes the results of qualifying a low cost, high quality mask making process for 90nm wafer production. The process uses a DUV laser-based mask writer to achieve low cost. Wafer photolithography process results using two masks fabricated with different mask making processes are presented, along with comparative electrical performance.
The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, a cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the Architecture from masks to wafers at 130 nm.
Aberrations, aberrations, here there everywhere but how do we collect useful data that can be incorporated into our simulators? Over the past year there have no less than 18 papers published in the literature discussing how to measure aberrations to answering the question if Zernikes are really enough. The ability to accurately measure a Zernike coefficient in a timely cost effective manner can be priceless to device manufacturers. Exposure tool and lens manufacturers are reluctant to provide this information for a host of reasons, however, device manufacturers can use this data to better utilize each tool depending on the level and the type of semiconductors they produce. Dirksen et al. first discussed the ring test as an effective method of determining lens aberrations in a step and repeat system, later in a scanning system. The method is based on two elements; the linear response to the ring test to aberrations and the use of multiple imaging conditions. The authors have been working to further enhance the capability on the test on the first small field 157 nm exposure system at International SEMATECH. This data was generated and analyzed through previously discussed methods for Z5 through Z25 and correlated back to PMI data. Since no 157nm interferemetric systems exist the lens system PMI data was collected at 248nm. Correlation studies have isolated the possible existence of birefringence in the lens systems via the 3-foil aberration which was not seen at 248nm. Imaging experiments have been conducted for various geometry's and structures for critical dimensions ranging from 0.13micrometers down to 0.10micrometers with binary and 0.07micrometers with alternating phase shift mask. The authors will review the results of these experiments and the correlation to imaging data and PMI data.
The mask error enhancement factor for contact holes is experimentally determined for 180 nm features under a variety of exposure conditions. Since its magnitude depends, in part, upon the slope of the aerial image, the value is calculated as a function of binary and phase shift masks, mask bias, and conventional and quadrupole illumination. The primary purpose is to compare experimental results to a simulation study and determine which simulation trends are accurately predicted. The results show that isolated contacts have lower MEEF than dense contacts but that dense contacts do not necessarily have the largest error factor. The magnitude of MEEF and the optimal bias that minimizes it are show to be accurately predicted.
Binary halftone chromeless PSM (CLM) can be described as a 100% transmission attenuated PSM (attPSM). The term 'binary halftone' refers to a novel OPC application to achieve the necessary CD control across the full feature-pitch range. We find that CLM is very complimentary -- with high numerical aperture (NA) and with off-axis illumination (OAI). In our wafer-printing experiment, we have achieved 70 nm through- pitch printing performance, using a KrF resist process. This was done in combination with a rule-based SB-OPC approach. At least 0.4 micrometer overlapped DOF with more than 6% exposure latitude has been attained for sub-100 nm printed features. For 2D complex patterns, we have observed a very strong optical proximity effect. CLM appears to be more sensitive to proximity effects, but less sensitive to lens aberration effects. Further experimentation and verification is required. Current mask-making processes appear to be capable of manufacturing CLM. We conclude that CLM has great potential to achieving production-worthy (lambda) /4 (or 0.2k1) lithography. The technology risk is neither in mask making nor in application software, but may be in reticle inspection and repair.
For lithography smaller that 180 nm using 248 nm steppers, phase-shifting lithography is becoming more routine. However, when applied to very small dimensions, OPC effects begin to become pronounced. We have design a new phase- shifting test structure for reticles to address these phase shifting distortions, and report on its use.
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