Mr. Shunsuke Koshihara Profile

Shunsuke Koshihara

at Hitachi High-Tech Corp

SPIE Involvement:

Conference Program Committee | Author

Publications (21)

SPIE Journal Paper | 12 September 2018

Need for LWR metrology standardization: the imec roughness protocol

Gian Francesco Lorusso, Takumichi Sutani, Vito Rutigliani, Frieda van Roey, Alain Moussa, Anne-Laure Charley, Chris Mack, Patrick Naulleau, Chami Perera, Vassilios Constantoudis, Masami Ikota, Toru Ishimoto, Shunsuke Koshihara

JM3, Vol. 17, Issue 04, 041009, (September 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041009

KEYWORDS: Metrology, Line width roughness, Scanning electron microscopy, Digital filtering, Atomic force microscopy, Standards development, Semiconductors, Image acquisition, Image quality, Electron microscopes

Read Abstract +

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: line width roughness (LWR) specifications are expected to be <2 nm in the near term, and to drop below 1 nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. We report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines [such as measurement box length >2 μm and the need to correct for scanning electron microscope (SEM) noise]. We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol—the imec roughness protocol—intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such as LWR, everyone speaks the same language, which is not currently the case.

Proceedings Article | 28 March 2018 Presentation + Paper

Presentation + Paper

The need for LWR metrology standardization: the imec roughness protocol

Gian Francesco Lorusso, Takumichi Sutani , Vito Rutigliani, Frieda van Roey, Alain Moussa, Anne-Laure Charley, Chris Mack, Patrick Naulleau, Vassilios Constantoudis , Masami Ikota , Toru Ishimoto, Shunsuke Koshihara

Proceedings Volume 10585, 105850D (2018) https://doi.org/10.1117/12.2294617

KEYWORDS: Line width roughness, Metrology, Standards development, Semiconductors, Scanning electron microscopy, Image acquisition, Atomic force microscopy, Finite element methods, Semiconducting wafers, Time metrology

Read Abstract +

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Proceedings Article | 19 March 2018 Presentation

Presentation

Impact of annealing temperature on DSA process: toward faster assembly kinetics (Conference Presentation)

Hyo Seon Suh, Akhil Nair, Paulina Rincon Delgadillo, Jan Doise, Gian Lorusso, Paul Nealey, Victor Monreal, Durairaj Baskaran, Yi Cao, Munirathna Padmanaban, Jin Li, Takeshi Kato, Takumichi Sutani, Toru Ishimoto, Masami Ikota, Shunsuke Koshihara

Proceedings Volume 10586, 105860T (2018) https://doi.org/10.1117/12.2299496

KEYWORDS: Directed self assembly, Annealing, Nanolithography, Lithography, Thin film manufacturing, Thin films, Resolution enhancement technologies, High volume manufacturing, Polymethylmethacrylate, Temperature metrology

Read Abstract +

Directed self-assembly (DSA) of block copolymer (BCP) thin films has been extensively researched as an alternative lithographic technology to enhance the resolution beyond the limitation of current lithography techniques.[1] One of the most critical factors need to be addressed for DSA process to be accepted at high volume manufacturing (HVM) is defect density of DSA pattern.[2] The defects of thermodynamically driven DSA process, such as the dislocation defects in LiNe flow, are known as kinetically trapped metastable structures.[3] Therefore, a key to eliminate those defects is to find out the effective kinetic pathway of assembly that enables BCP to reach to defect-free structure more easily. In addition to defect annihilation, easy pathway will also allow faster assembly, consequently reducing the cost of ownership of DSA process. The obvious approach for faster assembly in DSA process is to increase annealing temperature. In this study, we address the impact of annealing temperature on DSA process. First, increasing annealing temperature makes the free surface of a PS-b-PMMA film more PMMA preferential. Because of altered boundary condition at the top surface, more careful optimization of backfilling brush was required to maintain preferred orientation of BCP films. Second, the dimension of BCP is also affected by annealing temperature. Temperature dependency of BCP dimension was quantitatively investigated by CD-SEM and DSA-APPS Offline CD Measurement Software (Figure 1a). Based on the measured values, the dimension of chemical pattern is accordingly modified to achieve aligned DSA pattern (Figure 1b). We anticipate our finding from this study can be generally applied for other BCP systems. [1] Ruiz, Ricardo, Huiman Kang, François A. Detcheverry, Elizabeth Dobisz, Dan S. Kercher, Thomas R. Albrecht, Juan J. de Pablo, and Paul F. Nealey. "Density multiplication and improved lithography by directed block copolymer assembly." Science 321, no. 5891 (2008): 936-939. [2] Gronheid, Roel, Paulina Rincon Delgadillo, Hari Pathangi, Dieter Van den Heuvel, Doni Parnell, Boon Teik Chan, Yu-Tsung Lee et al. "Defect reduction and defect stability in IMEC's 14nm half-pitch chemo-epitaxy DSA flow." In SPIE Advanced Lithography, pp. 904905-904905. International Society for Optics and Photonics, 2014. [3] Hur, Su-Mi, Vikram Thapar, Abelardo Ramírez-Hernández, Gurdaman Khaira, Tamar Segal-Peretz, Paulina A. Rincon-Delgadillo, Weihua Li, Marcus Müller, Paul F. Nealey, and Juan J. de Pablo. "Molecular pathways for defect annihilation in directed self-assembly." Proceedings of the National Academy of Sciences 112, no. 46 (2015): 14144-14149.

Proceedings Article | 28 March 2017 Presentation + Paper

Presentation + Paper

Enabling CD SEM metrology for 5nm technology node and beyond

Gian Francesco Lorusso, Takeyoshi Ohashi, Astuko Yamaguchi, Osamu Inoue, Takumichi Sutani, Naoto Horiguchi, Jürgen Bömmels, Christopher Wilson, Basoene Briggs, Chi Lim Tan, Tom Raymaekers, Romain Delhougne, Geert Van den Bosch, Luca Di Piazza, Gouri Sankar Kar, Arnaud Furnémont, Andrea Fantini, Gabriele Luca Donadio, Laurent Souriau, Davide Crotti, Farrukh Yasin, Raf Appeltans, Siddharth Rao, Danilo De Simone, Paulina Rincon Delgadillo, Philippe Leray, Anne-Laure Charley, Daisy Zhou, Anabela Veloso, Nadine Collaert, Kazuhisa Hasumi, Shunsuke Koshihara, Masami Ikota, Yutaka Okagawa, Toru Ishimoto

Proceedings Volume 10145, 1014512 (2017) https://doi.org/10.1117/12.2257468

KEYWORDS: Metrology, Critical dimension metrology, Scanning electron microscopy, 3D metrology, Back end of line, Logic, Standards development, Germanium, Algorithm development, Process control, Resistance, Overlay metrology, Oxides, Etching, Statistical analysis

Read Abstract +

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

SPIE Journal Paper | 12 October 2016

Methodology for determining critical dimension scanning electron microscope measurement condition of sub-20 nm resist patterns for 0.33 NA extreme ultraviolet lithography

Nobuhiro Okai, Erin Lavigne, Keiichiro Hitomi, Scott Halle, Shoji Hotta, Shunsuke Koshihara, Atsuko Yamaguchi, Junichi Tanaka, Todd Bailey

JM3, Vol. 15, Issue 04, 044001, (October 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.4.044001

KEYWORDS: Extreme ultraviolet, Scanning electron microscopy, Critical dimension metrology, Electron microscopes, Extreme ultraviolet lithography, Electron beams, Image processing, Double patterning technology, Solids, Precision measurement

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SPIE Journal Paper | 19 July 2016

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Keiichiro Hitomi, Scott Halle, Marshal Miller, Ioana Graur, Nicole Saulnier, Derren Dunn, Nobuhiro Okai, Shoji Hotta, Atuko Yamaguchi, Hitoshi Komuro, Toru Ishimoto, Shunsuke Koshihara, Yutaka Hojo

JM3, Vol. 15, Issue 03, 034002, (July 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.3.034002

KEYWORDS: Optical proximity correction, Data modeling, Critical dimension metrology, Optical calibration, Scanning electron microscopy, Hybrid optics, Metals, Calibration, Instrument modeling, OLE for process control

Read Abstract +

Proceedings Article | 18 March 2016 Paper

Paper

Line width roughness accuracy analysis during pattern transfer in self-aligned quadruple patterning process

Gian Francesco Lorusso, Osamu Inoue, Takeyoshi Ohashi, Efrain Altamirano Sanchez, Vassilios Constantoudis, Shunsuke Koshihara

Proceedings Volume 9778, 97780V (2016) https://doi.org/10.1117/12.2218863

KEYWORDS: Line width roughness, Optical lithography, Line edge roughness, Transmission electron microscopy, Atomic force microscopy, Critical dimension metrology, Metrology, 3D metrology, Scanning electron microscopy, Process control, Etching, Signal to noise ratio, Image processing

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Proceedings Article | 19 March 2015 Paper

Paper

Methodology for determining CD-SEM measurement condition of sub-20nm resist patterns for 0.33NA EUV lithography

Nobuhiro Okai, Erin Lavigne, Keiichiro Hitomi, Scott Halle, Shoji Hotta, Shunsuke Koshihara, Junichi Tanaka, Todd Bailey

Proceedings Volume 9424, 94240H (2015) https://doi.org/10.1117/12.2175841

KEYWORDS: Extreme ultraviolet, Electron beams, Extreme ultraviolet lithography, Scanning electron microscopy, Precision measurement, Metrology, Image processing, Optical testing, Error analysis, Electron microscopes

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Proceedings Article | 2 April 2014 Paper

Paper

Precise CD-SEM metrology of resist patterns at around 20 nm for 0.33NA EUV lithography

Nobuhiro Okai, Erin Lavigne, Keiichiro Hitomi, Scott Halle, Shoji Hotta, Shunsuke Koshihara, Karen Petrillo, Atsuko Yamaguchi, Junichi Tanaka, Todd Bailey

Proceedings Volume 9050, 90501X (2014) https://doi.org/10.1117/12.2045375

KEYWORDS: Semiconducting wafers, Extreme ultraviolet, Electron beams, Extreme ultraviolet lithography, Photoresist processing, Critical dimension metrology, Metrology, Precision measurement, Photomasks, Image processing

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Proceedings Article | 31 March 2014 Paper

Paper

Hybrid OPC modeling with SEM contour technique for 10nm node process

Keiichiro Hitomi, Scott Halle, Marshal Miller, Ioana Graur, Nicole Saulnier, Derren Dunn, Nobuhiro Okai, Shoji Hotta, Atsuko Yamaguchi, Hitoshi Komuro, Toru Ishimoto, Shunsuke Koshihara, Yutaka Hojo

Proceedings Volume 9052, 90520W (2014) https://doi.org/10.1117/12.2047678

KEYWORDS: Optical proximity correction, Data modeling, Scanning electron microscopy, Critical dimension metrology, Metals, Instrument modeling, Calibration, Metrology, Logic devices, OLE for process control

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Proceedings Article | 5 April 2012 Paper

Paper

The study of high-sensitive and accurate metrology method by using CD-SEM

K. Ueda, S. Koshihara, T. Mizuno

Proceedings Volume 8324, 83242D (2012) https://doi.org/10.1117/12.915820

KEYWORDS: Finite element methods, Metrology, Smoothing, Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Time metrology, Process control, Semiconductors, Optics manufacturing

Read Abstract +

The earliest semiconductor device manufacturing employed optical microscopes for measurement and control of manufacturing process. The introduction of Critical Dimension Scanning Electron Microscope (CD-SEM) in 1984 provided a tremendous increase in capability for process monitoring and has been the standard for in-line metrology for over 25 years. The advantages of CD-SEM are highly accurate and stable measurement reproducibility at very specific locations throughout the device. The evolution of CD-SEM in Metrology has included improved resolution, development of advanced measurement and pattern recognition algorithms, all required by performance improvement demands from the market. Current conventional metrology using in-line CD-SEM involves measuring about ten points per wafer (one or more points per one chip). At a magnification of over x150k (Field of View is about 1μm²). In contrast, the area of measurement pattern on chip is much larger than the area of CD-SEM measurement (mm² : (on chip) versus μm² : (CDSEM measurement)). This would mean that the result of CD-SEM measurement is influenced by local pattern variation. The very stringent requirements placed on in-line Metrology for the last couple of technology nodes has produced an additional metrology methodology, beyond the CD-SEM, that involves large area measurements with very high precision for the most critical levels. We will refer to this methodology as "Macro Area Measurements". We reported the applicability of using a CD-SEM Macro Area Measurements methodology in SPIE2011 (797124). In the results, we were able to validate a new methodology that we called "Macro Area Measurement" which is demonstrated to successfully detect small process variations with the same throughput and reduced damage to the pattern. This time, we investigated the additional applicability of using a CD-SEM Macro Area Measurement methodology in this paper. The areas investigated focused on the following points: 1) Measurement repeatability related to CD-SEM measurement 2) Optimization of the measurement parameters using new function 3) Verification of Macro Area Measurement with a leading -edge device In the results, we are able to validate "Macro Area Measurements methodology which is demonstrated to successfully detect further small process variations with the almost same throughput and reduced damage to pattern.

Proceedings Article | 20 April 2011 Paper

Paper

The study of high-sensitivity metrology method by using CD-SEM

K. Ueda, S. Koshihara, T. Mizuno, A. Miura

Proceedings Volume 7971, 797124 (2011) https://doi.org/10.1117/12.878946

KEYWORDS: Metrology, Critical dimension metrology, Semiconducting wafers, Smoothing, Finite element methods, Optics manufacturing, Scanning electron microscopy, Algorithm development, Process control, Control systems

Read Abstract +

The earliest semiconductor device manufacturing employed optical microscopes for measurement and control of the manufacturing process. The introduction of the Critical Dimension Scanning Electron Microscope (CD-SEM) in 1984 provided a tremendous increase in capability for process monitoring and has been the standard for in-line metrology for over 25 years. The advantages of the CD-SEM are highly accurate and stable measurement reproducibility at very specific locations throughout the device. The evolution of the CD-SEM in Metrology has included improved resolution, development of advanced measurement and pattern recognition algorithms, all required by performance improvement demands from the market. Current conventional metrology using the in-line CD-SEM involves measuring about ten points per wafer (one point per one chip). at a magnification of over x150k(Field of View is about 1μm²). In contrast, the area of measurement pattern on chip is much larger than the area of CD-SEM measurement (mm² : (on chip) versus μm² : (CD-SEM measurement)). This would mean that the result of the CD-SEM measurement is influenced by local pattern variation. The very stringent requirements placed on in-line Metrology for the last couple of technology nodes has produced an additional metrology methodology, beyond the CD-SEM, that involves large area measurements with very high precision for the most critical levels. We will refer to this methodology as "Macro Area Measurements". We investigated the applicability of using a CD-SEM Macro Area Measurement methodology in this paper. The areas investigated focused on the following points: 1) Determining the optimum CD-SEM sampling plan for a macro area measurement. 2) Optimization of the measurement parameters. 3) Optimization of the measurement condition. 4) Verification of Macro Area Measurement with an FEM (Focus Exposure Matrix) wafer. In the results, we are able to validate a new methodology that we called "Macro Area Measurement" which is demonstrated to successfully detect small process variations with the same throughput and reduced damage to the pattern.

Proceedings Article | 2 April 2010 Paper

Paper

Improved recipe quality control: from development to mass production

Yukari Nakata, Shunsuke Koshihara, Hiroki Kawada, Kyoungmo Yang, Junichi Kakuta, Akemi Kono

Proceedings Volume 7638, 76382S (2010) https://doi.org/10.1117/12.846320

KEYWORDS: Image processing, Semiconducting wafers, Error analysis, Detection and tracking algorithms, Pattern recognition, Lithography, Product engineering, Metrology, Semiconductors, Manufacturing

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Proceedings Article | 2 April 2010 Paper

Paper

CD-SEM utility with double patterning

Benjamin Bunday, Pete Lipscomb, Shunsuke Koshihara, Shigeki Sukegawa, Yasuo Kawai, Yuki Ojima, Andy Self, Lorena Page

Proceedings Volume 7638, 76382U (2010) https://doi.org/10.1117/12.848546

KEYWORDS: Overlay metrology, Critical dimension metrology, Double patterning technology, Semiconducting wafers, Metrology, Lithography, Etching, Optical proximity correction, Scanning electron microscopy, Pattern recognition

Read Abstract +

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, and even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions and pitches continue to shrink, double patterning (DP) has become more common. Thus automatic recipe setup has needed to incorporate capabilities to deal simultaneously with two layers. This has the benefit of allowing the user to measure the two different CD populations and the image shift in the lithography (i.e., the overlay). Thus automatic recipe creation can be used to characterize the DP pattern for both CD and overlay. DesignGauge, the automatic recipe utility for Hitachi CG series CD-SEMs, is not only capable of offline recipe creation, but also can also directly transfer design-based recipes into standard CD-SEM recipes for use with DP processes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which improves production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, engineering time to generate recipes, and CD-SEM utilization. Another benefit of the application is that recipes are more robust than with conventional direct image-based pattern recognition. This paper explores the feasibility of matching a two-layer GDS pattern to features in an image, allowing for the more complex measurements involved in DP characterization. This work will evaluate DesignGauge with double litho double etch (DLDE DP), including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of the recipe creation, recipe execution, and verification of proper measurements of the dual CD populations and overlay.

Proceedings Article | 23 September 2009 Paper

Paper

SEM CD metrology on nanoimprint template: an analytical SEM approach

Justin Hwu, Sergey Babin, Lorena Page, Alex Danilevsky, Andy Self, Kazuhiro Ueda, Shunzuke Koshihara, Koichi Wago, Kim Lee, David Kuo

Proceedings Volume 7488, 74881W (2009) https://doi.org/10.1117/12.830699

KEYWORDS: Scanning electron microscopy, Image processing, Image analysis, Metrology, Line width roughness, Critical dimension metrology, Monte Carlo methods, Transmission electron microscopy, Quartz, Process modeling

Read Abstract +

Critical dimension metrology is the most needed feedback in nanofabrication and automatic CDSEM-based methods are by far the industrial standard for its well-established methodology and ease of programming and flexibility in measurement setup and operation. The dimensional measurements from SEMs consist of two steps, the first being the pixel based electron emission signal intensity profile generation and the second being the algorithm treatment on the generated intensity profile for the dimension determination. However, SEM metrology involves uncertainty of the measurement in the signal processing step, because the SEM signal formation is an extremely complex process depending on the pattern geometry, materials, detector setup, and beam voltage. Analytical SEMs are even less optimized for the task of quantitative metrology, especially at the CD ranging below 100 nm. In this work, we used an analytical SEM for CD metrology applications on quartz nanoimprint template from the perspective that only analytical SEM is accessible. The machine was tuned and beam characterization was done first to find the best reasonable condition for consistent manual operation using BEAMETR beam measurement pattern and software. The optimized beam condition set was then used for image collection on pitch pattern quartz template and the measurements were done using regular imaging processing and physical model based processing tool myCD. In order to discuss the spot size on the scan signal and the resulting influence on CD measurements, we used CHARIOT simulation software for simulated intensity profile as demonstration. The quartz template was then measured through a mask CDSEM for final data comparison. Selected sites were cross sectioned to reveal profile information as metrology comparison reference. Through our exercise, the metrology capability and fundamental limitation of analytical SEM operation with regular imaging processing was identified and the improvement using the physical modeling imaging process was verified.

Proceedings Article | 24 March 2009 Paper

Paper

Improving capability of recipe management on CD-SEM using recipe diagnostic tool

Kaoru Nishiuchi, Shinichi Nakano, Masaki Nishino, Kyoungmo Yang, Junichi Kakuta, Yukari Nakata, Shunsuke Koshihara

Proceedings Volume 7272, 72722F (2009) https://doi.org/10.1117/12.814972

KEYWORDS: Error analysis, Semiconducting wafers, Diagnostics, Pattern recognition, Metrology, Calibration, Lithography, Semiconductor manufacturing, Control systems, Computer aided design

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Proceedings Article | 23 March 2009 Paper

Paper

CD-SEM tool stability and tool-to-tool matching management using image sharpness monitor

Hideaki Abe, Yasuhiko Ishibashi, Yuichiro Yamazaki, Akemi Kono, Tatsuya Maeda, Akihiro Miura, Shunsuke Koshihara, Daisuke Hibino

Proceedings Volume 7272, 727210 (2009) https://doi.org/10.1117/12.813993

KEYWORDS: Critical dimension metrology, Monochromatic aberrations, Metrology, Scanning electron microscopy, Contamination, Visualization, Image resolution, Convolution, Electron beams, Image processing

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Proceedings Article | 5 April 2007 Paper

Paper

Major trends in extending CD-SEM utility

Benjamin Bunday, John Allgair, Kyoungmo Yang, Shunsuke Koshihara, Hidetoshi Morokuma, Alex Danilevsky, Cindy Parker, Lorena Page

Proceedings Volume 6518, 651835 (2007) https://doi.org/10.1117/12.714193

KEYWORDS: Pattern recognition, Critical dimension metrology, Metrology, Optical proximity correction, Semiconducting wafers, Reticles, Inspection, Scanning electron microscopy, Yield improvement, Detection and tracking algorithms

Read Abstract +

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, along with even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions continue to shrink, local line width variation influences the statistical confidence of a measured CD's representation of the process. A feature, called "Average CD (ACD)," measures multiple targets within the field of view (FOV). ACD allows not only measurements of a single data point representing one discrete feature, but also sampling of the mean and variance of the process. These two applications, automatic recipe creation and ACD, are combined in the second version of the DesignGauge software, which is available for the latest-generation Hitachi S-9380II CD-SEMs. DesignGauge V2 is not only capable of offline recipe creation and CD-SEM control, but it also has the ability to directly transfer design-based recipes into standard CD-SEM recipes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which yields much needed improvement to production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, reducing engineering time required to generate recipes, and improving CD-SEM utilization. Another benefit of the application is an improvement in recipe robustness over conventional direct image-based pattern recognition. This work will show an extensive evaluation of DesignGauge V2, including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation, and recipe execution. The impact of ACD will also be evaluated.

Proceedings Article | 5 April 2007 Paper

Paper

Advanced defect definition method using design data

Kyuhong Lim, Dilip Patel, Kyoungmo Yang, Shunsuke Koshihara, Lorena Page, Andy Self, Maurilio Martinez

Proceedings Volume 6518, 65184A (2007) https://doi.org/10.1117/12.711026

KEYWORDS: Inspection, Semiconducting wafers, Metrology, Scanning electron microscopy, Process control, Optical lithography, Integrated circuits, Integrated circuit design, Manufacturing, Defect detection

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Proceedings Article | 24 March 2006 Paper

Paper

Automated CD-SEM recipe creation: a new paradigm in CD-SEM utilization

Benjamin Bunday, William Lipscomb, John Allgair, Kyoungmo Yang, Shunsuke Koshihara, Hidetoshi Morokuma, Lorena Page, Alex Danilevsky

Proceedings Volume 6152, 61521B (2006) https://doi.org/10.1117/12.659759

KEYWORDS: Pattern recognition, Semiconducting wafers, Optical proximity correction, Scanning electron microscopy, Computer aided design, Lithography, Metrology, Scatterometry, Reticles, Precision measurement

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Proceedings Article | 24 May 2004 Paper

Paper

Prospects for using primary electron-based CD metrology

Bryan Rice, Gary Crays, Alex Danilevsky, Michael Grumski, Shunsuke Koshihara, Tadashi Otaka, Jeanette Roberts

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.544232

KEYWORDS: Control systems, Scanning electron microscopy, Critical dimension metrology, Semiconducting wafers, Metrology, Image processing, Transistors, Oxides, Silicon, Semiconductors

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Showing 5 of 21 publications

Conference Committee Involvement (13)

Metrology, Inspection, and Process Control XXXIX

24 February 2025 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVIII

26 February 2024 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVII

27 February 2023 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVI

25 April 2022 | San Jose, California, United States

Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV

22 February 2021 | Online Only, California, United States

Showing 5 of 13 Conference Committees

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