Over the past few years, deep neural networks have achieved state-of-the-art accuracy in a broad spectrum of applications. However, implementing deep networks in general purpose architectures is a challenging task as they require high computational resources and massive memory bandwidth. Recently, several digital neuromorphic chips have been proposed to address these issues. In this paper, we explore sixteen prominent rate based digital neuromorphic chip architectures, optimized primarily for inference. Specific focus is on: What is the motivation to design digital neuromorphic chips? Which optimizations play a key role in improving their performance? What are the main research trends in current generation chips?
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