CMOS image sensor (CIS) is used in various applications such as surveillance cameras, automobile cameras, mobile phones and digital single lens reflex (DSLR). The photodetectors used in the CIS are p-n junction photodiodes, pinned photodiodes, MOSFET-type photodetectors, and bipolar junction transistor-type photodetectors. A CMOS active pixel sensor (APS) with adjustable sensitivity is presented which uses MOSFET-type photodetector with a built-in transfer gate. The sensitivity of the APS using the MOSFET-type photodetector is much higher than that of the APS using the pn junction photodiode, since the MOSFET-type photodetector is composed of a floating-gate tied to an n-well and the photocurrent is amplified by the MOSFET. Although the APS using conventional MOSFET-type photodetector cannot control the current flowing through the channel, the APS using MOSFET-type photodetector with a built-in transfer gate can control the photocurrent by adjusting the pulse level of the transfer gate. Since the transfer gate controls the amount of electric charge that is transferred from the drain of the MOSFET to the integration node, the sensitivity of the APS can be adjusted by controlling the pulse level of the transfer gate. Using the high sensitivity characteristic of MOSFETtype photodetector and the function of transfer gate, the APS maintains high sensitivity under low intensity of illumination and adjusts to low sensitivity under high intensity of illumination. These results might be useful for extending the dynamic range of the APS using the MOSFET-type photodetector. The CMOS APS was designed and fabricated using 2-poly 4-metal 0.35 μm standard process and its performance was evaluated.
Effects of light intensity on disparity for depth extraction in monochrome CMOS image sensor with offset pixel apertures are investigated. The technology consumes less power, since it does not use external light sources. The offset pixel apertures are integrated in each pixel of the monochrome CMOS image sensor to acquire the disparity for depth extraction. Because the monochrome CMOS image sensor does not contain color filters, the height of the pixel is lower than that of the CMOS image sensor with color filters, resulting in a better disparity. The monochrome CMOS image sensor with offset pixel apertures was designed and fabricated using 0.11 μm CMOS image sensor process. Disparity of the sensor has been measured under various light intensities. The sensor might be useful for three-dimensional imaging in outdoor applications with a simple structure.
A CMOS image sensor with off-center circular apertures for two-dimensional (2D) and three-dimensional (3D) imaging was fabricated, and its performance was evaluated, including the results of 2D and 3D images. The pixel size, based on a four-transistor active pixel sensor with a pinned photodiode, is 2.8 μm × 2.8 μm. Disparate images as well as focused images for depth calculation can be obtained using the designed pixel pattern. The pixel pattern is composed of one white subpixel with a left-offset circular aperture, a blue pixel, a red pixel, and another white subpixel with a right-offset circular aperture. The proposed technique was verified by simulation and measurement results using a point light source. In addition, the depth image was implemented by calculating the depth information from the 2D images.
Effects of aperture size on the performance of CMOS image sensor with pixel aperture for depth extraction are investigated. In general, the aperture size is related to the depth resolution and the sensitivity of the CMOS image sensor. As the aperture size decreases, the depth resolution is improved and the sensitivity decreases. To optimize the aperture size, optical simulation using the finite-difference time-domain method was implemented. The optical simulation was performed with various aperture sizes from 0.3 μm to 1.1 μm and the optical power with the incidence angle as a function of the aperture size was evaluated. Based on the optical simulation results, the CMOS image sensor was designed and fabricated using 0.11 μm CMOS image sensor process. The effects of aperture size are investigated by comparison of the simulation and the measurement results.
The 3-dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. Many techniques have been reported for 3D imaging using various methods such as time of fight (TOF), stereo vision, and structured light. These methods have limitations such as use of light source, multi-camera, or complex camera system. In this paper, we propose the offset pixel aperture (OPA) technique which is implemented on a single chip so that the depth can be obtained without increasing hardware cost and adding extra light sources. 3 types of pixels including red (R), blue (B), and white (W) pixels were used for OPA technique. The aperture is located on the W pixel, which does not have a color filter. Depth performance can be increased with a higher sensitivity because we use white (W) pixels for OPA with red (R) and blue (B) pixels for imaging. The RB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Previously, we proposed the pixel aperture (PA) technique based on the depth from defocus (DFD). The OPA technique is expected to enable a higher depth resolution and range compared to the PA technique. The pixels with a right OPA and a left OPA are used to generate stereo image with a single chip. The pixel structure was designed and simulated. Optical performances of various offset pixel aperture structures were evaluated using optical simulation with finite-difference time-domain (FDTD) method.
In this paper, we propose a pixel averaging current calibration algorithm for reducing fixed pattern noise due to the deviation of bolometer resistance. To reduce fixed pattern noise (FPN), averaging current calibration algorithm by which output current of each bolometer reference pixel is averaged by the averaging current calibration is suggested. The principle of algorithm is that average dark current of reference pixel array is subtracted by a dark current of each active pixel array. After that, the current difference with information of pixel deviation is converted to voltage signal through signal processing. To control the current difference of pixel deviation, a proper calibration current is required. Through this calibration algorithm, nano-ampere order dark currents with small deviations can be obtained. Sensor signal processing is based on a pipeline technique which results in parallel processing leading to very high operation. The proposed calibration algorithm has been implemented by a chip which is consisted of a bolometer active pixel array, a bolometer reference pixel array, average current generators, line memories, buffer memories, current-to-voltage converters (IVCs), a digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). Proposed bolometerresistor pixel array and readout circuit has been simulated and fabricated by 0.35μm standard CMOS process.
Recently, CMOS image sensors (CISs) have become more and more complex because they require high-performances such as wide dynamic range, low-noise, high-speed operation, high-resolution and so on. First of all, wide dynamic range (WDR) is the first requirement for high-performance CIS. Several techniques have been proposed to improve the dynamic range. Although logarithmic pixel can achieve wide dynamic range, it leads to a poor signal-to-noise ratio due to small output swings. Furthermore, the fixed pattern noise of logarithmic pixel is significantly greater compared with other CISs. In this paper, we propose an optimized linear-logarithmic pixel. Compared to a conventional 3-transistor active pixel sensor structure, the proposed linear-logarithmic pixel is using a photogate and a cascode MOSFET in addition. The photogate which is surrounding a photodiode carries out change of sensitivity in the linear response and thus increases the dynamic range. The logarithmic response is caused by a cascode MOSFET. Although the dynamic range of the pixel has been improved, output curves of each pixel were not uniform. In general, as the number of devices increases in the pixel, pixel response variation is more pronounced. Hence, we optimized the linear-logarithmic pixel structure to minimize the pixel response variation. We applied a hard reset method and an optimized cascode MOSFET to the proposed pixel for reducing pixel response variation. Unlike the conventional reset operation, a hard reset using a p-type MOSFET fixes the voltage of each pixel to the same voltage. This reduces non-uniformity of the response in the linear response. The optimized cascode MOSFET achieves less variation in the logarithmic response. We have verified that the optimized pixel shows more uniform response than the conventional pixel, by both simulation and experiment.
A 3dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. In this paper, extraction of depth information for 3D imaging using pixel aperture technique is presented. An active pixel sensor (APS) with in-pixel aperture has been developed for this purpose. In the conventional camera systems using a complementary metal-oxide-semiconductor (CMOS) image sensor, an aperture is located behind the camera lens. However, in our proposed camera system, the aperture implemented by metal layer of CMOS process is located on the White (W) pixel which means a pixel without any color filter on top of the pixel. 4 types of pixels including Red (R), Green (G), Blue (B), and White (W) pixels were used for pixel aperture technique. The RGB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RGB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Size of the pixel for 4-tr APS is 2.8 μm × 2.8 μm and the pixel structure was designed and simulated based on 0.11 μm CMOS image sensor (CIS) process. Optical performances of the pixel aperture technique were evaluated using optical simulation with finite-difference time-domain (FDTD) method and electrical performances were evaluated using TCAD.
In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.
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