The 22nm Spacer Self Aligned Double Patterning (SADP) process developed at Applied Materials' Maydan Technology Center was used to characterize small particle defects in the four critical steps
of the process flow: Lithography, APF Etch, Spacer Deposition, Spacer Open. Small Particle defect
contamination poses a risk to yield in each of the SADP process steps (Lithography, Deposition and
Etch) and requires an understanding of their sources and impact on each subsequent step. The defect
inspection was carried out using two different inspection platforms; DFinderTM which is designed
for detection of 3D defects and UVision TM 3 which is designed for detection of 2D defects. Small
particle defects (smaller than 60nm), in the Lithography and APF Etch process steps were shown to
become "killer" defects at the Spacer Open step. More study is needed to develop inspection
strategies based on a wider range of defect types.
As semiconductor process design rules continue to shrink, the ability of optical inspection tools to separate between true
defects and nuisance becomes more and more difficult. Therefore, monitoring Defect of Interest (DOI) become a real
challenge (Figure 1). This phenomenon occurs due to the lower signal received from real defects while noise levels remain
almost the same, resulting in inspection high nuisance rate, which jeopardizes the ability to provide a meaningful, true
defect Pareto. A non-representative defect Pareto creates a real challenge to a reliable process monitoring (Figure 4).
Traditionally, inspection tool recipes were optimized to keep data load at a manageable level and provide defect maps with
~10% nuisance rate, but as defects of interest get smaller with design rule shrinkage, this requirement results in a painful
compromise in detection sensitivity. The inspection is usually followed by defect review and classification using scanning
electron microscope (SEM), the classification done manually and it is performed on a small sample of the inspection defect
map due to time and manual resources limitations. Sample is usually 50~60 randomly selected locations, review is
performed manually most of the times, and manual classification is performed for all the reviewed locations.
In the approach described in this paper, the inspection tool recipe is optimized for sensitivity rather than low nuisance rate
(i.e. detect all DOI with compromising on a higher nuisance rate). Inspection results with high nuisance rate introduce new
challenges for SEM review methodology & tools. This paper describe a new approach which enhances process monitoring
quality and the results of collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and
GLOBALFOUNDRIES® utilizing Applied Materials ADRTrueTM & SEMVisionTM capabilities.
The study shows that the new approach reveals new defect types in the Pareto, and improves the ability to monitor the
process and identify excursion for low magnitude defect of interest.
KEYWORDS: Semiconducting wafers, Line edge roughness, Wafer inspection, Finite element methods, Polarization, Inspection, Critical dimension metrology, Deep ultraviolet, Metrology, Process control
As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.
Minute variations in advanced VLSI manufacturing processes are well known to
significantly impact device performance and die yield. These variations drive the need
for increased measurement sampling with a minimal impact on Fab productivity.
Traditional discrete measurements such as CDSEM or OCD, provide, statistical
information for process control and monitoring. Typically these measurements require a
relatively long time and cover only a fraction of the wafer area.
Across array across wafer variation mapping ( AWV) suggests a new approach for high
throughput, full wafer process variation monitoring, using a DUV bright-field inspection
tool. With this technique we present a full wafer scanning, visualizing the variation
trends within a single die and across the wafer.
The underlying principle of the AWV inspection method is to measure variations in the
reflected light from periodic structures, under optimized illumination and collection
conditions. Structural changes in the periodic array induce variations in the reflected
light. This information is collected and analyzed in real time.
In this paper we present AWV concept, measurements and simulation results.
Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied
Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and
normal wafers. AWV and CDSEM results are presented to reflect CD variations within a
memory array and across wafers.
Ilan Englard, Raf Stegen, Peter Vanoppen, Ingrid Minnaert-Janssen, Ted der Kinderen, Erik van Brederode, Frank Duray, Jeroen Linders, Denis Ovchinnikov, Rich Piech, Claudio Masia, Noam Hillel, Erez Ravid, Ofer Rotlevi, Amir Wilde, Saar Shabtay, Zach Telor, Robert Schreutelkamp
Increase of Depth of Focus (DOF) and higher Numerical Aperture (NA), make of immersion lithography a sub-50nm
technology node enabler. At the same time it introduces a range of new defect types, also known as immersion defects.
According to the ITRS roadmap, the Smallest Defect Of Interest (SDOI) for the 45nm node has a size of 30nm [1] which
is the minimal defect size which poses risk to the integrity of the post litho chain processes. A novel approach of
Immersion Defectivity Baseline creation and monitoring has been developed for the 45nm technology node by ASML,
supported by Applied Materials. An Immersion Defectivity Baseline consists of: a qualified stack, a dedicated
defectivity reticle, a Defect Inspection Tool with an optimized inspection recipe, a Defect Review SEM with an
optimized defect review recipe and a defect qualification scheme. The new approach to Immersion Defectivity Baseline
creation is based on the combined capabilities of highest resolution bright-field inspection and SEM (Scanning Electron
Microscopy) review that are available today, with a unique qualification methodology using printed programmed defects
that cover the full printable size range. The inspection tool's SDOI detection sensitivity has been optimized for
engineering, production as well as monitoring modes, with negligible nuisance rate and basic classification capability
followed by highly accurate SEM review and classification. As a result, it enables a stringently controlled, highly
efficient, automated defect classification for baseline monitoring and increased productivity. The SEM material analysis
sub-apparatus complete the control loop for baseline creation and excursion control. This paper presents a protocol for
Immersion Defectivity Baseline creation and control methodologies used for the latest ASML immersion scanner.
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