Graphene has extraordinary electro-optic properties and is therefore a promising candidate for monolithic photonic devices such as photodetectors. However, the integration of this atom-thin layer material with bulky photonic components usually results in a weak light-graphene interaction leading to large device lengths limiting electro-optic performance. In contrast, here we demonstrate a plasmonic slot graphene photodetector on silicon-on-insulator platform with high-responsivity given the 5 µm-short device length. We observe that the maximum photocurrent, and hence the highest responsivity, scales inversely with the slot width. Using a dual-lithography step, we realize 15 nm narrow slots that show a 15-times higher responsivity per unit device-length compared to photonic graphene photodetectors. Furthermore, we reveal that the back-gated electrostatics is overshadowed by channel-doping contributions induced by the contacts of this ultra-short channel graphene photodetector. This leads to quasi charge neutrality, which explains both the previously-unseen offset between the maximum photovoltaic-based photocurrent relative to graphene’s Dirac point and the observed non-ambipolar transport. Such micrometer compact and absorption-efficient photodetectors allow for short-carrier pathways in next-generation photonic components, while being an ideal testbed to study short-channel carrier physics in graphene optoelectronics.
The performance shortcomings of multipurpose compute engines have stirred recent excitement in specialized processors, preempted by GPUs. Simultaneously, computational complexity theory NP 'hard' problems scaling as O(n^k) require new hardware solutions. This presents an opportunity for photonic information processors (PIP) building on photonic integration through recent foundry developments. The value proposition for PIPs exist via optical parallelism, small capacitive charging of OE devices, 10's of ps short propagation delays, a natural convolution via optical interference, and an O(n)-scaling Fourier transform. Based on a recently developed photonic NxN router, here we present two photonic processors; a) the residual arithmetic nanophotonic computer (RANC), and b) a reconfigurable graph processor, the latter being a computing-in-switching (CIS) paradigm. PIPs operate with time-of-flight, once the processor is configured (e.g. setting phase), which is on the order of 10-100 ps given the mm-scale photonic integration footprints. This high bandwidth, however challenges the electronic-optic I/O bottleneck. To address this, we further discuss an optical front-end DAC with <100 ps delay enabled by a 2x2 electro-optic switch.
Residue number system (RNS) enables dimensionality reduction of an arithmetic problem by representing a large number as a set of smaller integers, where the number is decomposed by prime number factorization. These reduced problem sets can then be processed in- dependently and in parallel, thus improving computational efficiency and speed. Here we show an optical RNS hardware representation based on integrated nanophotonics. The digit-wise shifting in RNS arithmetic is expressed as spatial routing of an optical signal in 2×2 hybrid photonic-plasmonic switches. Here the residue is represented by spatially shifting the input waveguides relative to the routers’ outputs, where the moduli are represented by the number of waveguides. By cascading the photonic 2×2 switches, we design a photonic RNS adder and a multiplier forming an all-to- all sparse directional network. The advantage of this photonic arithmetic processor is the short (10’s ps) computational execution time given by the optical propagation delay through the integrated nanophotonic router. Furthermore, we show how photonic processing in- the-network leverages the natural parallelism of optics such as wavelength-division-multiplexing in this RNS processor. A key application for such a photonic RNS engine is the functional analysis of convolutional neural networks.
Here we proposed three adiabatically coupled waveguides (ACW), while the outer waveguides perform as a two-mode system analogous to ground- and excited- states and the middle waveguide is same as dark-state in a three-level-atomic system. Thanks to the dark-state, intermediate waveguide is based on plasmonic Indium thin oxide (ITO) as an active structure. Our simulation indicates a power consumption of 40 atto-joule with 50 dB modulation depth. In addition, our ACW plasmonic modulator provides high-speed operation as high as 5.4 THz and insertion loss as low as 0.45 dB. The proposed device is crucial for futuristic of optical short-reach interconnects.
In this paper we benchmark various interconnect technologies including electrical, photonic, and plasmonic options. We contrast them with hybridizations where we consider plasmonics for active manipulation devices, and photonics for passive propagation integrated circuit elements, and further propose another novel hybrid link that utilizes an on chip laser for intrinsic modulation thus bypassing electro-optic modulation. Link benchmarking proves that hybridization can overcome the shortcomings of both pure photonic and plasmonic links. We show superiority in a variety of performance parameters such as point-to-point latency, energy efficiency, capacity, ability to support wavelength division multiplexing, crosstalk coupling length, bit flow density and Capability-to-Latency-Energy-Area Ratio.
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