Proceedings Article | 3 March 2016
G. Reed, R. Topley, A. Khokhar, D. Thompson, S. Stanković, S. Reynolds, X. Chen, N. Soper, C. Mitchell, Y. Hu, L. Shen, G. Martinez-Jimenez, N. Healy, S. Mailis, A. Peacock, M. Nedeljkovic, F. Gardes, J. Soler Penades, C. Alonso-Ramos, A. Ortega-Monux, G. Wanguemert-Perez, I. Molina-Fernandez, P. Cheben, G. Mashanovich
KEYWORDS: Waveguides, Silicon photonics, Silicon, Annealing, Optical alignment, Signal attenuation, Semiconducting wafers, Multiplexers, Optical fibers, Transceivers
This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.
