Arrays of Geiger-mode avalanche photodiodes (GmAPDs) are fabricated on a new type of engineered substrates with an epitaxial layer grown on silicon-on-insulator (SOI) wafers. The SOI-based structure facilitates rapid die-level bump bonding of the GmAPD array to a CMOS readout integrated circuit (ROIC) followed by substrate removal to make a backilluminated image sensor. To fabricate the engineered substrate, a commercial substrate with a 70-nm-thick SOI layer is implanted with BF2 ions to create a p+-doped passivation layer on the light illumination surface. Subsequently, a lightly p-doped silicon layer on which the GmAPD will be fabricated is grown using a homoepitaxy process. This approach allows for the use of chip-level hybridization to CMOS, avoiding the high cost and demanding wafer flatness and smoothness requirements of wafer-scale 3D integration processes. The new process yields cleaner wafers and allows for tighter control of detector layer thickness compared to the previous process. GmAPDs fabricated on 5-μm-thick epitaxial silicon have over 70% photon detection efficiency (PDE) when 532 nm light is focused into the center 3 μm of the device with an oxide layer that remains after substrate removal. With an anti-reflective coating, the PDE can be improved.
We have developed a new approach for rapid die-level hybridization of backside-illuminated silicon avalanche photodiode (APD) arrays to CMOS readout integrated circuits (ROICs). APD arrays are fabricated on a custom silicon-on-insulator (SOI) wafer engineered with a built-in backside contact and passivation layer. The engineered APD substrate structure facilitates uniform APD substrate removal by selective etching at the die level after bump bonding. The new integration process has the following advantages over wafer-level 3D integration: 1) reduced cost per development cycle since a dedicated full-wafer ROIC fabrication is not needed, 2) compatibility with existing ROICs that are in chip-format from previous fabrication runs, and 3) accelerated schedule. The new approach is applied to produce 32×32 100-μm-pitch silicon GmAPD arrays. Electrical performance of the APD arrays show 100% pixel connectivity and excellent yield before and after substrate removal.
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