We demonstrate the performance of broadband, low loss, and compact three-mode converter and (de)multiplexer utilizing an asymmetric trijunction splitter, multimode interferometer, and a phase shifter; all are designed using on subwavelength grating technology (SWG) and built-in a silicon-on-insulator platform for the first time to the best of our knowledge. SWG enables the flexibility of refractive index engineering for more operating bandwidth and compactness compared with conventional counterparts. The designed device is capable of converting and (de)multiplexing three different input modes TE0, TE1, and TE2 into a fundamental TE0 output mode. The three-dimensional finite-difference time-domain simulation results confirm that the designed device has a low loss of 1 dB and the crosstalk reaches −65 dB over a broad wavelength of 160 nm (1470 to 1630 nm) in the C-band range with an overall size of the designed device is 95 × 4 μm2.
A three-step modified signed-digit (MSD) adder is proposed which can be optically implmented using binary logic gates. The proposed scheme depends on encoding each MSD digits into a pair of binary digits using a two-state and multi-position based encoding scheme. The design algorithm depends on constructing the addition truth table of binary-coded MSD numbers and then using Karnaugh map to achieve output minimization. The functions associated with the optical binary logic gates are achieved by simply programming the decoding masks of an optical shadow-casting logic system.
Optical shadow-casting (OSC) technique is seriously being considered as an efficient method that is capable of optically implementing two-operand parallel logic gates and array logic systems. The sixteen logic functions for two binary patterns (variables) are optically realizable in parallel by properly configuring an array of 2×2 light emitting diodes. In this paper, we propose an enhanced OSC technique for implementing four-operand parallel logic gates. The proposed system is capable of performing 216 logic functions by simply programming the switching mode of an array of 4×4 light emitting diodes in the input plane. This leads to an efficient and compact realization scheme when compared to the conventional two-operand OSC system.
A new modified signed-digit (MSD) addition algorithm based on binary logic gates is proposed for parallel computing. It is shown that by encoding each of the input MSD digits and flag digits into a pair of binary bits, the number of addition steps can be reduced to two. The flag digit is introduced to characterize the next low order pair (NLOP) of the input digits in order to suppress carry propagation. The rules for two-step addition of binary coded MSD (BCMSD) numbers are formulated that can be implemented using optical shadow-casting logic system.
A two-step trinary signed-digit (TSD) multiplication technique based on digit grouping and smart pixel assignment is proposed. In this technique, the partial products are generated directly without recoding the TSD numbers. This nonrecoding based TSD multiplication technique results in significant reduction in the number of symbolic substitution rules employed in the algorithm. Several spatial encoding schemes are introduced and their relative performance in the presence of additive noise is discussed.
The trinary signed-digit (TSD) number system is of interest for ultra fast optoelectronic computing systems since it permits parallel carry-free addition and borrow-free subtraction of two arbitrary length numbers in constant time. In this paper, a simple coding scheme is proposed to encode the decimal number directly into the TSD form. The coding scheme enables one to perform parallel one-step TSD arithmetic operation. The proposed coding scheme uses only a 5-combination coding table instead of the 625-combination table reported recently for recoded TSD arithmetic technique.
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