As the Extreme Ultraviolet (EUV) lithography ecosystem is being actively mapped out to enable sub-7nm
design rule devices, there is an immediate and imperative need to identify the EUV reticle (mask) inspection
methodologies [1]. The introduction of additional particle sources due to the vacuum system and potential growth of
haze defects or other film or particle depositions on the reticle, in combination with pellicle uncertainty pose unique
inspection challenges when compared to 193i reticles.
EUV reticles are typically inspected with optical reticle-inspection tools. However, if there is a pellicle on the
EUV mask which is non-transmissive to the optical wavelengths used in the reticle inspection tools, then there is a need
for alternative inspection methodologies based on inspection of printed wafers. In addition, due to the potential new
defect mechanisms associated with the EUV reticles, fabs are looking for additional methods to re-qualify reticles in
production using printed wafer inspections. The printed wafer inspection methodology is referred to as “Reticle Print
Verification” or “Reticle Print Check.” This paper discusses these alternative inspection methodologies that are being
developed in collaboration with imec using an advanced broadband plasma (BBP) patterned wafer optical inspection
(KLA-Tencor 3905) and e-beam review systems (KLA-Tencor eDR7280).
Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires
accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process
steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper
presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection
(ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM)
review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to
an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical
defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point
at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an
excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1)
Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain
understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to
develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the
advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory
devices.
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