Single-exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for argon fluoride immersion (ArFi)-based multiple patterning approaches for printing the most critical features in semiconductor devices. However, the dimensional scaling of EUV lithography patterns is hampered by stochastic effects, resulting in rough patterns and increased defectivity. A promising solution to mitigate these stochastic pattern variations is complementing top–down EUV lithography with bottom–up directed self-assembly (DSA) of block copolymers (BCPs). We investigated an EUV + DSA complementary process for the rectification of pitch 28-nm line/space (L/S) patterns on high-volume manufacturing compatible processing tools. We found that several DSA material and process parameters contribute to minimize the roughness of the rectified patterns. In particular, the BCP size and film thickness are the most critical parameters. In terms of defectivity, a combination of optical inspection and e-beam review pointed out that dislocations are not a major concern for EUV + DSA patterning due to the fast assembly kinetics. Instead, bridge and cluster defects are the main defect modes and minimum defectivity can be achieved by controlling the geometry of the guide pattern. Finally, the impact of pattern density multiplication by DSA was assessed by comparing the performance of the current EUV + DSA rectification process to the ArFi + DSA technology, both for generating a pitch 28 nm L/S pattern.
Semiconductor processing has been advancing from the nano to the atomic scale. For atomic-scale processing, the plasma source need to be precisely controlled to minimize damage, such as UV radiation damage, ion-induced damage, and charge accumulation damage. In this presentation, we will introduce an Ultra Low Electron Temperature (ULET) plasma (Te < 0.5 eV) as a novel plasma source enabling us to perform damage-free plasma processing. We will also explain how to produce the ULET plasma. It is demonstrated that charge accumulation even in a patten with high aspect ratio is almost eliminated, and graphene remains undamaged in the ULET plasma, while it is heavily damaged in conventional plasma processes. The ULET plasma shows great promise for applications in atomic-scale plasma processing.
Future advanced semiconductor manufacturing processes are introducing significant patterning challenges. These challenges are coming together with additional requirements for sustainable, low Global Warming Potential/ low toxicity /low fine particle emissions. As a result, new solutions in terms of process integrations, molecules used for patterning modules, and overall stack of materials will have to meet those requirements while staying compatible with high-volume manufacturing (cost, availability, throughput, and overall patterning performance). Although specific process steps such as capacitor patterning for DRAM or 3D NAND high aspect ratio oxide etch are heavily scrutinized steps in terms of emissions and patterning challenges, many applications, including logic, integrate hundreds of steps where the patterning of 10 to 30nm-thick layers requiring fluorine-containing gases. Although independently accounting for a modest amount of emissions, their sheer counts makes them a major contributor to CO2 equivalent emissions. In this work, the cumulative impact of these low aspect-ratio patterning steps will be modelled through the imec.netzero program model. Then, the impact of a few sustainability-optimized solutions, such as low temperature etching for ultra-thin layer or stack optimization will be assessed.
To continue the future of dynamic random-access memory (DRAM) manufacturing with EUV and high NA EUV, alternative techniques for nanofabrication are required to reduce the cost and simplify the processes. In this report, we present the results of the development of a single mask solution with 0.33NA EUV lithography for two important layers, bit-line-periphery (BLP) and storage-node-landing-pad (SNLP), in DRAM manufacturing. The methodology has been established for our examination and assessment of the process window (PW) of the critical dimensions (CD) and the defectivity of the SNLP and BLP layers. Based on this methodology, a pitch 34nm DRAM has been optimized with the spin-on metal oxide resist (MOR) and dark field of a binary mask. We obtained the large overlapping PW of CDs (with a depth of focus of 119nm and an exposure latitude of 25% at a dose-to-size of 89.4mJ cm-2) in the free-defect ranges (20mJ cm-2). We achieved around ~22% dose reduction using the same processes with spin-on MOR applied to the new design of a low-n mask. We observed a pitch of 32nm SNLP and BLP with a single mask layer due to a low-n mask. Additionally, the process window discovery (PWD) methodology for defect inspection in the large area of SNLP and BLP shows good progress which can be applied for optimized conditions. We believe that our results show the resolution limit of 0.33NA lithography for the single mask print SNLP-BLP and 0.55NA EUV is needed for the next generations of DRAM.
Continuous scaling by extreme ultraviolet (EUV) lithography is tightening the patterning requirements for photoresist materials. Specifically, chemically amplified resists (CAR) are facing significant challenges to keep supporting the patterning needs. In view of this, complementing EUV lithography with directed self-assembly (DSA) of block copolymers offers interesting opportunities to enable the use of CAR towards ultimate resolution. As DSA decouples the resist patterning performance from the final pattern quality, roughness and defects in the resist pattern can be rectified. Here, we discuss the impact of material and process parameters on the rectification performance by DSA, both for line-space and hexagonal contact hole arrays.
Sustainability is gaining momentum as countries and companies announce targets for net-zero carbon emissions by 2050. imec has created a bottom-up model using tool data, process recipes, and integrated wafer process flows to create a virtual fab. With this model, it is possible to quantify the environmental impact of manufacturing integrated circuit (IC) chips for current and future logic and memory technology modes. In this paper, the model is used to identify areas with the highest environmental impact. It is important to reduce the impact of both lithography and etch since together they are responsible for 45% of total CO2 equivalent emissions associated with fabricating an N3 logic node wafer. For lithography, two approaches to reducing the environmental impact will be described: one concentrates on tool consumption and the other on process choices to maximize throughput. For etch, the focus is on reducing overall gas consumption and improving wafer material stacks to minimize fluorocarbon use. Translating patterning process changes into emission numbers will enable informed process choices for future and contribute to a shift towards net-zero semiconductor manufacturing.
To further enable device scaling in HVM, new patterning materials are needed to meet the more stringent requirements such as line width and edge roughness (LWR and LER), dose sensitivity, pattern collapse, etch resistance and defectivity. The continuous progression of the shrinking of resist feature sizes will be accompanied by the scaling-down of the resist film thickness to prevent pattern collapse and to compensate for low depth-of-focus for high-NA EUV lithography. However, if we reduce the resist film thickness, we must also reduce the underlayer (UL) hardmask film thickness for optimum pattern transfer. As an alternative to spin-on underlayers, deposited ULs can be a potential candidate as it is possible to produce very thin uniformly deposited ULs, with the freedom to incorporate different elements to improve adhesion and modify etch selectivity. In this paper, we will discuss deposited ULs with film thickness scaled down to 3.5 nm for EUV lithography patterning as well as etch performance for pitch 32 and 28 line/space structures. We will also discuss about the possibility to modify the ULs to match the surface energy of the photoresist in use in order to minimize pattern collapse. Additionally, with scaled-down deposited ULs, we were able to obtain very similar post-litho unbiased roughness values (LWR 2.23 nm and LER 1.7 nm) as 10 nm spin-on reference UL (LWR: 2.26 nm and LER 1.66 nm). We will discuss more such details in terms of surface roughness, dose sensitivity, post-litho and post-etch LWR, LER, pattern collapse and defectivity in the presentation. Such ULs could become useful for high-NA EUV lithography when the litho stack is expected to scale down in thickness.
For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, the transition from 193 nm to 13.5 nm light is severely limiting the number of photons produced by a given source power, leading to photon shot noise in EUV patterns. In addition, inhomogeneous distribution of components inside conventional photoresists is adding to the printing variability, especially when critical dimensions continue to shrink. As a result, stochastic issues leading to rough, non-uniform, and potentially defective patterns have become a major challenge for EUV lithography. A promising solution for this top-down patterning approach is complementing it with bottom-up directed self-assembly (DSA) of block copolymers. In combination with 193i lithography, DSA of lamellae forming block copolymers has previously shown favorable results for defining dense line-space patterns using LiNe flow.1 In this study, we investigate the complementarity of EUV + DSA for rectification of pitch 28 nm line-space patterns. Roughness and defectivity are critical factors that need to be controlled to make these patterns industrially relevant. We look at the impact of DSA material and processing parameters on line edge roughness and line width roughness in order to identify and mitigate the origins of pattern roughness. On the other hand, we also assess the different types of defect modes that are observed by means of optical defect inspection and ebeam review, and study the root causes for their formation. To wrap-up, the benefits of 1X DSA versus 3X DSA are presented by comparing EUV + DSA to LiNe flow.
Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.
As the limits of EUV single exposure direct printing are being explored there is a need for etch processes that can transfer small features and reduce defectivity. The implementation of high numerical aperture (NA) EUV scanner tool will allow for printing of sub-10 nm features in a single exposure. However, it reduces the depth of focus, thus requires thinner photoresist coatings. In preparation for high NA (0.55) we explore the etch implications of thin EUV photoresists. Here we show two different strategies for bridge defect reduction during etch and break elimination with selective deposition during the etch process.
Directed self-assembly (DSA) process has been introduced and developed for more than a decade as one of the alternative advanced patterning techniques in the semiconductor industry. Block copolymer (BCP) is self-assembling into the desired pattern on the lithographically defined pre-pattern on the wafer. Such a bottom-up approach is used to define the pattern which is typically hard to achieve with the traditional top-down approach. As an example, the density of the pattern can be increased with DSA by the factor of 3 or 4 from the 193i lithography pattern. Although similar dimension becomes now accessible with EUV lithography, DSA keeps its benefit; the structure is simply defined by the phase separation of materials rather than the complex light-matter interactions as required for EUV resist patterning. In this presentation, we will discuss the synergetic impact of the combination of EUV and DSA.
The goal of this work is to prepare process readiness towards High NA EUV lithography, by using 0.33NA exposures on
NXE3400B scanner. We focus on photoresists, underlayers and etch processes mitigation of P24nm Line Space patterns.
Etch transfer has been validated for Metal Oxide Resist (MOR). Furthermore, we investigate challenges to accelerate
Chemically Amplified Resist (CAR) P24nm Line Space processes. Also, here, promising patterning results have been
achieved. Thin film metrology-friendly methods like Atomic Force Microscopy (AFM) have been performed to
characterize and improve the CAR-based etch processes.
Results for the self-assembly of lamellar silicon-containing high-χ block copolymers (BCP) with innovative neutral top-coat design are presented. We demonstrate that these materials and associated processes are compatible with a standard lithographic process, and oriented toward a potential high volume manufacturing. We show that this dedicated technology is able to guarantee the stability and planarity of the stack even at elevated self-assembly bake temperatures, and opens new opportunity in the fields of 3D BCPs stacks. Finally, we show interesting results for the etch-transfer of a lamellar BCP in silicon.
In this work, we present our recent achievements on the integration and transfer etching of a novel silicon-containing high-χ block copolymer for lines/spaces applications. Developed carbo-silane BCPs are synthesized under industrial conditions and present periodicities as low as 14 nm. A full directed self-assembly by graphoepitaxy process is shown using standard photolithography stacks and all processes are performed on 300 mm wafer compatible tools. Specific plasma processes are developed to isolate perpendicular lamellae and sub-12 nm features are finally transferred into silicon substrates. The quality of the final BCP hard mask (CDU, LWR, LER) are also investigated. Finally, thanks to the development of dedicated neutral layers and top-coats allowing perpendicular orientations, it was possible to investigate plasma etching experiments on full-sheets at 7 nm resolution, opening the way to the integration of these polymers in chemoepitaxy stacks.
X. Chevalier, P. Coupillaud, G. Lombard, C. Nicolet, J. Beausoleil, G. Fleury, M. Zelsmann, P. Bezard, G. Cunge, J. Berron, K. Sakavuyi, A. Gharbi, R. Tiron, G. Hadziioannou, C. Navarro, I. Cayrefourcq
Properties of new block copolymers systems, specifically designed to reach large periods for the features, are compared to the ones exhibited by classical PS-b-PMMA materials of same dimensions. Conducted studies, like free-surface defects analysis, mild-plasma tomography experiments, graphoepitaxy-guided structures, etch-transfer… indicate much better performances, in terms of achievable film-thicknesses with perpendicular features, defects levels, and dimensional uniformities, for the new system than for the classical PS-b-PMMA. These results clearly highlight unique and original solutions toward an early introduction of DSA technology into large lithographic nodes.
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