The lithography industry has historically striven to improve resolution by reducing wavelength and increasing the lens’ numerical aperture (NA). The introduction of 0.33 NA extreme ultraviolet (EUV) lithography into high-volume manufacturing (HVM) represents the largest jump in resolution ever achieved by the industry. However, even this resolution is not sufficient for the patterns required for beyond the 2 nm logic technology node. This is due to low contrast and the diffraction limit of current EUVL scanners for the mask patterns required for these nodes. Instead, the resolution must be improved by increasing the NA. This will also increase the contrast of patterns which had insufficient contrast at 0.33 NA, which will in turn improve LCDU and defectivity. This change is not without its challenges though. Increasing the NA from 0.33 to 0.55 will cause a significant reduction in depth of focus. In addition, stronger mask 3D effects can cause pattern dependent shifts in best focus. As a result, the common overlapping process window of several critical patterns can become strongly diminished. The use of anamorphic optics will require two separate half-field exposures to obtain the equivalent of a single full-field exposure on current EUV and DUV scanners. For some chip sizes, this will require stitching two half-fields together to pattern the full chip area. In previous technology nodes, the process window could be improved using SMO and SRAFs. In addition, over the last five years, the industry has put significant effort into studying alternative absorbing materials. These materials can significantly reduce the mask 3D effects by reducing the thickness of the absorber. The use of alternative absorbers alone will not be sufficient for improving the overlapping process window. Instead, several techniques must be simultaneously utilized in order to ensure sufficient overall process window. Optimization of overlapping process windows is critical for successful insertion of high-NA EUVL into HVM. In this paper we analyze how the process window of critical patterns can be optimized by using different optimizations. We will show for realistic mask designs how process window can be improved in different process steps. Double exposure from half-field stitching will also be included in the process evaluation. We use both rigorous and compact modeling in a complimentary fashion for overall process optimization analysis. All techniques presented in this paper accurately model the anamorphic, centrally obscured optics of the upcoming next-generation high-NA scanners.
While technology is being developed, design rules undergo a number of revisions. An initial lithography model built with test patterns before the revisions inherently become inaccurate for the revised patterns. Preparing a new test layout and updating a lithography model every time design rules are revised is not practical, and cannot be a solution. We prepare some synthetic patterns in addition to initial test patterns. Synthetic patterns originate from popular test pattern generator (TPG), while projected design rule changes are taken into account. A challenge is to sort out the synthetic patterns which are really necessary in building a generic lithography model when they are used together with test patterns. Each pattern, either synthetic or test, is identified in image parameter set (IPS) space. For each test pattern in IPS space, two concentric spheres are drawn; outer one indicating the region where revised versions of test pattern may exist, and inner one indicating the region which is well covered by test pattern alone. Synthetic patterns that reside in the region bounded by the two spheres are kept, while the others are dropped. Clustering is now performed on test patterns and synthetic patterns separately, and representative pattern is drawn from each cluster. When a set of representative patterns are used to build a lithography model in 10nm memory devices, it achieves 43.5% lower CD root mean square error (RMSE) for revised design layout compared with only using a set of initial test patterns.
Fast computation of process variation band (PVB) is critical for several lithography applications such as yield estimation, hotspot detection, mask optimization, and etc. Conventionally, PVB is computed by lithography simulation that is very slow and can only be applied for a small part of a chip. These small parts of a chip are identified through a pattern matching process, where unseen patterns are often missed. We explore conditional generative adversarial networks (cGANs), a couple of machine learning models, for predicting PVB with high speed and sufficient accuracy. In our proposed method, we divide a full-chip into several small clips and then predict PVB for a small region of interest at the center of each clip. Experiments show that our proposed method can successfully predict PVB for more than 98% of the patterns with an average accuracy, and speedup of 86%, and 500 times, respectively, compared to the rigorous lithography simulation.
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