We observed plasmon resonance peaks at two different wavelengths by combining plasmon wave from aluminum (Al) and gold (Au) nano-particles (NP). We model the absorption characteristics of two nano particles placed with nano meter scale gap using RF module of COMSOL 5.3 modeling program. The coupled plasmon layer has two peaks at 525 and 640 nm, which are different from the constituent individual metal plasmon layers of Al and Au NPs with peak at 450 nm and 700 nm respectively. Good agreement exits between modeling data with experimental results.
We report a significant increase in electroluminescence from GaSb based Long-wave infrared
(LWIR) inter band cascade (IC) LED device by substrate thinning and isolating pixel from each
other. We use bottom emitting LWIR LED array for isolating each pixel by chemical etching. We
observed 300% increase in light emission power of etched device. We fabricated an IC LED device
with thirty cascade active/injection layers with InAs/Ga1-xInxSb/InAs quantum well (QW) active
region.
We report a significant increase in electroluminescence from GaSb based mid-wave infrared
inter band cascade (IC) LED device through coupling with localized surface plasmon layer. Thin
Au Plasmon layer of 20 nm thickness is deposited on top anode electrode by e-beam evaporation
technique. Surface Plasmon enhancement effects result is 100% increase in light output for 50
μm square mesa device. We fabricated an IC LED device with nine cascade active/injection
layers with InAs/Ga1-xInxSb/InAs quantum well (QW) active region.
We report the IR electroluminescence in two wavelength bands, 3-4 micron (MWIR) and 8-9
micron (LWIR) regions. The epitaxial structure was grown on an n-type GaSb substrate with the
MWIR quantum well (QW) region on top of LWIR QW region and a 0.5 μm contact layer grown in
between the two QW regions. We measured the light emission from the top surface of the device
with different grating structures. We fabricated square mesas varying from 50 to 200 microns on a
side. Both room temperature and cryogenic temperature results show emission in the wavelength
regions as designed.
We report here the electroluminescence in the range of 3-4.5 μm and 6-10 μm from
Sb-based type II interband quantum cascade structure LED devices. We measured the light
emission from the top surface of the device with different grating structures. We used
different etch depths for the grating formation. The light-current-voltage (LIV)
characteristics measured at both room and cryogenic temperatures show that the device
with 45 degree angle grating and 1.0 μm deep etch onto the GaSb surface has the highest
emission power.
Electroluminescence in the range of 7-9 μm is observed from an Sb-based type II interband quantum cascade
structure. The LED structure has 30 active/injection periods. We have studied both top emitting and flip-chip mount
bottom emitting LED devices. For room temperature operation, an increase, saturation and decrease in light output occur
at successively higher injection currents. An increase of about ten times in light output occurs when device is operated at
77 K compared to room temperature operation. This increase is attributed to reduced Auger non-radiative recombination
at lower temperatures. We varied indium mole fraction between 18-30% in the device active regions. An increase in
light output is observed for lower indium mole fraction. These devices can be used for high temperature simulation in an
infrared scene generation experiment.
We designed and fabricated 64x64 supper lattice light emitting diode (SLED) array with
peak emission wavelength of 3.8 micron. The light emission is observed from the bottom side of
the device through the substrate. The CMOS driver circuit is fabricated in the 130 nm IBM 8HP
SiGe process. The unit cells were designed to source up to 100mA to the LED. These unit cells
can be individually addressable, and have analog drive and memory that can operate at a 1 kHz
array refresh rate. We use supper lattice epitaxial active region LED structures grown on n-type
GaSb substrates. After initial mesa etching and contact metal deposition, the LED array is flip
chip mounted on the LCC package. The light emission is observed from the LED array by InSb
focal plane MWIR camera and the apparent black body temperature is measured.
We report here the light emission from IR interband-cascade (IC) Type-II-super lattice LED structures. The light emission is observed from bottom side through the substrate. We employed two different IC epitaxial structures for the LED experiments consisting of 9 or 18 periods of active super lattice gain regions separated by multilayer injection regions. The light output (and the voltage drop) of the LEDs is observed to increase with decrease of device operating temperature from room temperature (300 K) to liquid helium temperature (4 K). At low temperature the light emission as well as voltage drop has peak like structure with device injection currents. We observed a red shift in peak wavelength of LED emission with higher DC injection current where as blue shift due to pulsed injection current.
We report here the light emission from IR interband-cascade (IC) Type-II-super lattice LED structures. We employed two different IC epitaxial structures for the LED experiments consisting of 9 or 18 periods of active super lattice gain regions separated by multilayer injection regions. The light output (and the voltage drop) of the LEDs is observed to increase with increase of number of IC active regions in the device. The voltage drop decreases with increase of mesa size and light emission increases with mesa sizes. We have made 8x7 2-D LED array flip-chip bonded to fan out array. The black body emissive temperature is 650 and 1050 K for LED operation at room and liquid nitrogen temperature respectively. A comparison of different IR sources for scene generation is presented.
We at Army Research Laboratory (ARL) have developed 2xD light emitting device (LED) arrays for possible application in infrared (IR) scene projection experiments. These LEDs emit light in the 3-4 μm wavelength region with peak at 3.75 μm when operate at room temperature. The epitaxial structure for LED was grown on GaSb substrate by molecular beam epitaxial (MBE) technology. Mesa sizes ranging from 30-100 μm diameters were used in the device fabrication. By comparing with radiation from blackbody source, we found that the brightness temperature of the infrared LED is in the range of 300-600 K. We obtained very good uniformity in device current and voltage (I-V) characteristics. This paper discusses the LED array design, fabrication and evaluation results.
Corrugated quantum well IR photodetector (QWIP) focal plane arrays (FPAs) with cutoff wavelength of 11.2 and 16.2 micrometers were fabricated and tested. Each detector array has 256 X 256 pixel elements, indium bumped to a direct injection readout circuit manufactured by Rockwell Science Center. The rest of the supporting electronics were designed and built in-house to provide biases and clock functions to the FPAs. IR imageries with good aesthetic attributes were obtained from both FPAs. For the 11.2 micrometers FPA, background limited IR performance (BLIP) was obtained at 63 K under F/2 optics, consistent with the test results of a large area detector. This operating temperature is substantially higher than the grating coupled arrays with comparable cutoff wavelengths. On the other hand, the optics of the present camera were not optimized for wavelengths beyond 14 micrometers . As a result, the BLIP temperature for the 16.2 micrometers FPA, observed to be 38 K, was somewhat lower than the expected 42 K from the single detector characterization. Despite the reduced detector volume of a C-QWIP structure, the measured internal quantum efficiency remains to be high, being 20.5 percent and 25.4 percent at 2 V bias for the 11.2 micrometers and the 16.2 micrometers FPA, respectively.
A process for fabrication of low-frequency, low-noise, low- power silicon JFETs for cryogenic operation has been developed. COmmercially available silicon JFETs exhibit very high low frequency and 1/f noise at liquid nitrogen temperature. We report on process optimization and effect of high temperature oxidation and drive-in process on noise performance of these devices. These silicon JFETs were designed for operation at 77K. In this paper, we report the noise performance and its relation to the well-known complex oxygen-vacancy. A center that has a trap level of 0.18 eV below the conduction band. These devices were developed for use in the photo-diode assembly of NASAs Gravity Probe B mission telescope.
A corrugated quantum well IR photodetector (C-QWIP) focal plane array (FPA) with cutoff at 11.2 micrometers has been fabricated and characterized. The C-QWIP array uses total internal reflection to couple normal incident light into the pixels. The processing steps involve only one chemical etching, one optional reactive ion etching, and one ohmic contact metalization. The detector array has 256 X 256 pixel elements, indium bumped to a direct injection readout circuit. The photocurrent to dark current ratio measured in this FPA, on which the noise equivalent temperature difference depends, is consistent with that of a large area test sample. The array shows good responsivity uniformity of 5.2 percent with no extra leakage resulted from array processing. The estimated noise equivalent temperature difference of this array, excluding the readout noise, is 17 mK at T equals 63 K. The fact that this FPA can be operated at a temperature similar to those of standard QWIP arrays with much shorter wavelengths shows that the C-QWIP structure can greatly increase array performance.
Reactive ion etching (RIE) is commonly used, as a process tool, for the etching of polysilicon, silicon dioxide, silicon nitride and other thin film deposits. One of the key requirements of the etching process is the accurate end-point detection of the process. There exist a number of process monitoring techniques for end-point detection, these however are costly to install and maintain. In response to this requirement, a new method for end-point detection of polysilicon topography etching in single wafer plasma reactive ion etcher is presented here, which incurs no added costs. The method is based upon experimental results correlating polysilicon etching end-point with the increase in the cathodic self-bias voltage developed across the substrate. It is shown that the end-point of polysilicon topography etching can be found by monitoring the first derivative of the self- bias voltage with time. Using this method it has been demonstrated that accurate end-point detection of polysilicon etching can be obtained with a residue free field, near- vertical polysilicon profile and critical dimension loss of less than 0.05 micrometer.
Hole trapping phenomena by substrate hot carrier (SHC) stressing and ionizing radiation are compared. Similar effects on device characteristics such as transconductance change, threshold voltage (Vt) shift etc due to SHC stressing and ionizing radiation are observed. Less radiation induced Vt shift is observed for SHC stressed device than that due to virgin device. Though the hole traps due to SHC stressing and ionizing irradiation anneal with applied field, their annealing behavior is markedly different. It is due to the fact that the hole trap distribution is different for SHC stressing condition than that due to ionizing irradiation.
A simple technique based on the measurement of gate induced drain leakage current (Idl) is developed to measure the radiation induced charge in the metal oxide semiconductor transistor. After irradiation Idl of n-channel MOS transistors decreases while that of p-channel devices increases. The change of leakage current at higher tunneling fields is proportional to the increase of hole trap density in the gate oxide region. The leakage current measurement technique is an useful tool for characterizing radiation effects in MOS transistors because at high biases Idl is dependent on the increase of oxide charge while independent of the interface states. It depends on gate and drain overlap geometry and independent of the channel length. Hence Idl measurement technique is advantageous over threshold voltage technique which depends on the channel length.
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