Mr. Michael Jurisch Profile

Michael Jurisch

at Institut für Mikroelektronik Stuttgart

SPIE Involvement:

Author

Publications (5)

Proceedings Article | 19 February 2020 Paper

Nanoimprint lithography for augmented reality waveguide manufacturing

Christine Thanner, Anna Dudus, Dominik Treiblmayr, G. Berger, M. Chouiki, Stephan Martens, Michael Jurisch, Julian Hartbaum, Martin Eibelhuber

Proceedings Volume 11310, 1131010 (2020) https://doi.org/10.1117/12.2543692

KEYWORDS: Nanoimprint lithography, Manufacturing, Augmented reality, Semiconducting wafers, Waveguides, Optics manufacturing, Electron beam lithography, Polymers, High volume manufacturing, Nanostructures

Read Abstract +

Wafer-level nanoimprint lithography (NIL) has increasingly become a key enabling technology to support new devices and applications across a wide range of markets. Leading manufacturers of augmented reality (AR) devices, optical sensors and biomedical chips are already utilizing NIL and realizing the benefits of this technology, including the ability to mass manufacture micro- and nano-scale structures down with a maximum degree of freedom for the device dimensions. Another key advantage of this replication based technology is, given by the fact that even complex structures which require precise and time consuming fabrication methods can be transferred to mass manufacturing in an efficient semiconductor manufacturing line. Additionally, for many devices especially for optical applications the replicated layer can be directly used as functional layer in the product. Today NIL is considered as decisive process step for a number of emerging products, including AR waveguides. With increasing volumes the scaling of the production lines is crucial for most economical implementation of NIL. In particular for scaling to production lines using 200mm or even 300mm wafer sizes, the whole process chain has to be established. This is in particular a focus for AR devices requiring highly complex structures with tight specifications. Thus best efforts for master fabrication are crucial to obtain best performing devices. For smaller substrates, typically full area masters are used to manufactured and used for the NIL process. However, as the masters are mainly fabricated by sequential processes the costs scale with the pattern area. For 200mm and 300mm it has been proven to be viable option to start with single high-quality devices and scale them by step and repeat (SR) NIL to fully populated waferscale masters and subsequently to use those for volume manufacturing on wafer-level. The wafer-level production itself requires then reliable replication of working stamps and wafer level nanoimprinting of these multiple devices on a single wafer. As a result it is key for the high volume manufacturing to have a thorough understanding of all required pattering and replications steps to enable these large area manufacturing lines.

Proceedings Article | 27 May 2010 Paper

W-CMOS blanking device for projection multibeam lithography

Michael Jurisch, Mathias Irmscher, Florian Letzkus, Stefan Eder-Kapl, Christof Klein, Hans Loeschner, Walter Piller, Elmar Platzgummer

Proceedings Volume 7748, 774815 (2010) https://doi.org/10.1117/12.865478

KEYWORDS: Electrodes, Lithography, Tungsten, Etching, Semiconducting wafers, Silicon, Nanofabrication, Projection devices, Photomasks, Projection systems

Read Abstract +

Proceedings Article | 23 September 2009 Paper

Charged particle multi-beam lithography evaluations for sub-16nm hp mask node fabrication and wafer direct write

Elmar Platzgummer, Christof Klein, Peter Joechl, Hans Loeschner, Martin Witt, Wolfgang Pilz, Joerg Butschke, Michael Jurisch, Florian Letzkus, Holger Sailer, Mathias Irmscher

Proceedings Volume 7488, 74881D (2009) https://doi.org/10.1117/12.832156

KEYWORDS: Photomasks, Ions, Semiconducting wafers, Lithography, Nanofabrication, Silicon, Particles, Electronics, Nanostructures, Electron beams

Read Abstract +

Proceedings Article | 23 September 2009 Paper

3D Si aperture-plates combined with programmable blanking-plates for multi-beam mask writing

Florian Letzkus, Mathias Irmscher, Michael Jurisch, Elmar Platzgummer, Christof Klein, Hans Loeschner

Proceedings Volume 7488, 74883C (2009) https://doi.org/10.1117/12.829630

KEYWORDS: Silicon, Etching, Electrodes, Semiconducting wafers, Photomasks, Lithography, 3D metrology, Standards development, Beam shaping, Oxides

Read Abstract +

Proceedings Article | 20 October 2008 Paper

Deflection unit for multi-beam mask making

Florian Letzkus, Joerg Butschke, Mathias Irmscher, Michael Jurisch, Wolfram Klingler, Elmar Platzgummer, Christof Klein, Hans Loeschner, Reinhard Springer

Proceedings Volume 7122, 712235 (2008) https://doi.org/10.1117/12.801401

KEYWORDS: Etching, Silicon, Electrodes, Semiconducting wafers, Lithography, Aluminum, Mask making, Optical alignment, Switching, Line edge roughness

Read Abstract +

Two main challenges of future mask making are the decreasing throughput of the pattern generators and the insufficient line edge roughness of the resist structures. The increasing design complexity with smaller feature sizes combined with additional pattern elements of the Optical Proximity Correction generates huge data volumes which reduce correspondingly the throughput of conventional single e-beam pattern generators. On the other hand the achievable line edge roughness when using sensitive chemically amplified resists does not fulfill the future requirements. The application of less sensitive resists may provide an improved roughness, however on account of throughput, as well. To overcome this challenge a proton multi-beam pattern generator is developed [1]. Starting with a highly parallel broad beam, an aperture-plate is used to generate thousands of separate spot beams. These beams pass through a blanking-plate unit, based on a CMOS device for de-multiplexing the writing data and equipped with electrodes placed around the apertures switching the beams "on" or "off", dependent on the desired pattern. The beam array is demagnified by a 200x reduction optics and the exposure of the entire substrate is done by a continuous moving stage. One major challenge is the fabrication of the required high aspect deflection electrodes and their connection to the CMOS device. One approach is to combine a post-processed CMOS chip with a MEMS component containing the deflection electrodes and to realize the electrical connection of both by vertical integration techniques. For the evaluation and assessment of this considered scheme and fabrication technique, a proof-of-concept deflection unit has been realized and tested. Our design is based on the generation of the deflection electrodes in a silicon membrane by etching trenches and oxide filling afterwards. In a 5mm x 5mm area 43,000 apertures with the corresponding electrodes have been structured and wired individually or in groups with aluminum lines. The aperture-plate for shaping the beams has been aligned and mounted on top of the blanking-plate. Afterwards this sandwich has been fixed on a base-plate with a pin plug as interface. The electrical connection has been performed with a standard chip bonding process to the aluminum pads on the blanking-plate. Finally, the proof-of-concept deflection unit was evaluated in a test bench. The results of electrical- and exposure tests are presented and discussed in detail.

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years