Electronics advancement demands integration of large number of transistors /capacitors in a very small chip area. Thus, small feature size fabrication is a critical issue and precise fabrications of features under nano scale require advanced lithographic and etching techniques. In this paper, MOS capacitor with TiN metal-gate and HfO2 dielectric layer was fabricated in a world class clean-room lab in KTH. There, state-of-the art lithography stepper, advanced etching machines and all important clean-room fabrication facilities were used for successful fabrication of the nano-dimension MOS capacitor, whose detailed experimental procedures and results are exhaustively dealt in this report.
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