We report a 20 nm half-pitch self-aligned double patterning (SADPP) process based on a resist-core approach. Line/space 20/20 nm features in silicon are successfully obtained with CDvariation, LWR and LER of 0.7 nm, 2.4 nm and 2.3 nm respectively. The LWR and LER are characterized at each technological step of the process using a power spectral density fitting method, which allows a spectral analysis of the roughness and the determination of unbiased roughness values. Although the SADP concept generates two asymmetric populations of lines, the final LLWR and LER are similar. We show that this SADP process allows to decrease significantly the LWR and the LER of about 62% and 48% compared to the initial photoresist patterns. This study also demonstrates that SADP is a very powerful concept to decrease CD uniformity and LWR especially in its low-frequency components to reach sub-20 nm node requirements. However, LER low-frequency components are still high and remain a key issue tot address for an optimized integration.
With the constant decrease of semiconductor device dimensions, gate line edge roughness (LER) becomes an important source of device variability. Gate LER originates from photoresist (PR) LER that is partially transferred into the gate during plasma etching. A plasma treatment is typically used to reduce the PR LER before the transfer. LER control at the nanometer scale also requires accurate measurements. We have recently developed a technique for LER measurement based upon atomic force microscopy (AFM). In this technique, the sample is tilted at about 45 deg and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The AFM technique is applied to the study of a pattern transfer into a gate stack starting from untreated PR, PR treated by conventional HBr plasma, and PR treated by HBr/O 2 plasma followed by a bake at 150°C. It is found that the plasma etching reduces the LER at each etching step. The reduction is more important when starting from untreated PR which has the highest initial LER. However, the final LER in the Si layer remains significantly smaller when starting with cured PR, especially with PR cured by an HBr/O 2 plasma treatment followed by a bake at 150°C.
The major issue related to line width roughness (LWR) is the significant LWR of the photoresist patterns printed by 193-nm lithography that is partially transferred into the gate stack during the subsequent plasma etching steps. The strategy used today to overcome this issue is to apply postlithography treatments to reduce photoresist pattern LWR before transfer. In this article, we investigate the impact of various plasma treatments (HBr, H 2 , He, Ar) on the minimization of the LWR of dense and isolated photoresist patterns and its transfer during gate patterning. To do so, we use critical dimension scanning electron microscopy measurements combined with power spectrum density fitting method to extract unbiased LWR values and provide a spectral analysis of the LWR. We show that plasma treatments that lead to carbon redeposition from the gas phase on the resist pattern sidewalls are less efficient to reduce LWR than plasma treatments where the redeposition is limited. Among all plasma chemistries, H 2 plasmas seem very promising to decrease resist LWR in the whole spectral range, while maintaining square resist profiles. In addition, we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.
KEYWORDS: Line edge roughness, Etching, Plasma, Atomic force microscopy, Plasma treatment, Silicon, Critical dimension metrology, Vacuum ultraviolet, System on a chip, Photoresist materials
With the constant decrease of semiconductor device dimensions, gate Line Edge Roughness (LER) becomes one of the most important sources of device variability and needs to be controlled well below 2 nm for the future technological nodes of the semiconductor roadmap. Gate LER originates from photoresist (PR) LER that is partially transferred into the gate during the plasma etch process. A plasma treatment is typically used to reduce the PR LER before the transfer. We have shown that an HBr plasma treatment reduces the LER by about 30% whereas an HBr/O2 plasma treatment followed by a bake at 150°C can reduce the LER further, by about 50%. The LER control at the nanometer scale also requires accurate measurements. We have developed a technique for LER measurement based upon Atomic Force Microscopy (AFM). In this technique, the sample is tilted at about 45° and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The small radius of curvature of the tip together with the low noise level of a laboratory AFM result in high resolution images. Half profiles and LER values on all the height of the sidewalls are extracted from the 3D images using a procedure that we developed. The AFM technique is applied to the study of a full pattern transfer into a simplified gate stack starting from untreated PR, PR treated by a conventional HBr plasma, and PR treated by an HBr/O2 plasma followed by a bake at 150°C. It is found that plasma etching reduces the LER at each etching step. The reduction is much more important when starting from untreated PR which has the highest initial LER. However, the final LER in the Si layer remains significantly smaller when starting with cured PR, especially with PR cured by an HBr/O2 plasma treatment followed by a bake at 150°C.
With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter
that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future
technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is
known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be
partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the
noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an
experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an
accurate estimation of the CDSEM noise level and extraction of unbiased LWR.
In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length,
fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H2, He, Ar), and
also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We
show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon
species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H2 that limit carbon
redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show
that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the
high frequency roughness components are lost.
Scanning Spreading Resistance Microscopy (SSRM) and Scanning Capacitance Microscopy (SCM) are two techniques based upon the atomic force microscope (AFM), which are used to obtain two-dimensional carrier maps of a semiconductor device’s cross-section. As all AFM techniques, they require probes with sharp tips to get good resolution images. Additionally, a hard and wear resistant tip material is needed to withstand the extreme mechanical stress tips are submitted to while a good conductivity is necessary for the characterization of highly doped areas of modern devices. In this work, several types of materials are evaluated based upon their mechanical and electrical characteristics: metals, hardmetals, conductive oxides and doped diamond. Commercial metal and diamond coated silicon tips are currently used (only diamond for SSRM). However, tips with thin metal coatings wear fast while the high resistivity of diamond limits the dynamic range. In both cases, the radius of curvature of coated tips is fairly large limiting the resolution. Probes with tips made out of TiN, a hardmetal, were manufactured using the molding technique. Using these tips, an ohmic point contact was obtained on Si. In SSRM mode, resistivity contrast was observed for the first time for a metallic tip. TiN tips also proved to be hard enough to penetrate the oxide and obtain SSRM images on InP. A good contrast and a monotonic behavior on n-type silicon in the absence of bias were obtained in SCM. The wear rate of TiN tips is lower than that of coated Si tips. However, despite their high hardness, TiN tips wore fast under high pressure and the tips died after a few SSRM scan lines on Si, and after a few images on InP.
At the Belgian institute IMEC techniques for the production of electrically conductive atomic force microscope (AFM) probes are developed. To facilitate handling of the fragile probes, holder chips are required. The assembly of such holder chips, which can be split up into the application of solder paste, the positioning of the holder chip and the soldering of the chip, is a crucial manufacturing step, that, until now, was performed manually for economic reasons. With the help of a modular micro assembly tool, developed by the Institute for Machine Tools and Industrial Management (iwb) of the Technische Universitaet Muenchen, an economical automated assembly of the holder chips was developed. Thanks to our integrated sensor technology, even the automated assembly onto the extremely fragile membranes of moulded AFM probes was possible. In particular, the dispensing process of the solder paste onto the membranes was improved by the integration of a non-contact sensor for the needle clearance.
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