Ilan Englard, Raf Stegen, Erik Van Brederode, Peter Vanoppen, Ingrid Minnaert-Janssen, Frank Duray, Ted der Kinderen, Gazi Tanriseven, Inge Lamers, Mireia Blanco Mantecon, Lior Levin, Eitan Binyamini, Nurit Raccah, Shalev Dror, Eran Valfer, Ofer Rotlevi, Robert Schreutelkamp, Rich Piech
Immersion lithography offers great benefit for advanced technology nodes but at the same time poses a great challenge.
Along with hyper NA values, which increase the scanner resolution, new types of imaging process related defects
emerge. These new defects are related to water, top coating, resist and BARC in the litho process. Root cause analysis of
the so-called wet defects (immersion) versus the so-called dry defects (non immersion-related) becomes crucial in any
immersion lithography related defect reduction program. Manual and eventually automated classification of defects can
be used to analyze the data and monitor baselines. Furthermore, a robust Automatic Defect Classification (ADC)
increases productivity and decreases the wafer cycle time.
This article outlines a methodological approach for wet and dry defect classification that employs rule-based ADC and
enables the generation of an immersion induced defect library for fast baseline improvement and excursion monitoring.
The work described in this article has been performed at ASML using Applied Materials' SEMVision G3 FIB automated
defect review and analysis tool.
Challenges of the new nanometer processes have complicated the yield enhancement process. The systematic yield loss component is increasing, due to the complexity and density of the new processes and the designs that are developed for them. High product yields can now only be achieved when process failure rates are on the order of a few parts per billion structures. Traditional yield ramping techniques cannot ramp yields to these levels and new methods are required.
This paper presents a new systematic approach to yield loss pareto generation. The approach uses a sophisticated Design-of-Experiments (DOE) approach to characterize systematic and random yield loss mechanisms in the Back End Of the Line (BEOL). Sophisticated Characterization Vehicle (CV)TM test chips, fast electrical test and Automatic Defect Localization (ADL) are critical components of the method. Advanced statistical analysis and visualization of the detected and localized electrical defects provides a comprehensive view of the yield loss mechanisms. In situations where the defects are not visible in a SEM of the structure surface, automated FIB and imaging is used to characterize the defect. The combined approach provides the required resolution to appropriately characterize parts per billion failure rates.
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