As design rule continues to shrink, resolution enhancement techniques (RET) such as optical proximity correction (OPC) become more and more complex to enable design printability. As we know, typically integrated circuit (IC) layouts are simple shapes such as rectangles. However, high spatial frequency components of the mask spectrum that are not captured by the low-pass pupil result in a rounded image. In addition, the diffusion process in the postexposure bake (PEB) step makes the wafer rounding effects worse. This means that it is difficult to get the wafer image to match the design exactly at corners, even with the most aggressive OPC methodology. Therefore, pre-OPC site placement optimization is necessary to achieve high quality wafer images. In this work, a contour-based OPC methodology is proposed to minimize the time consumption in pre-OPC simulation site placement optimization and OPC job running. Rounded target contours that best describe the real intended wafer result are used as the target during OPC correction. By comparing classical OPC recipe-driven target point placement and contour-based OPC methodology, it is found that contour-based OPC methodology can achieve comparable image quality in a shorter turn around time (TAT) with fewer engineer resources.
Traditional double-exposure lithography (DEL) or double-patterning lithography (DPL) methodologies stem most from the resolution enhancement standpoint. A single mask with high feature densities is split into two exposure steps, each with lower feature densities that can be easily resolved. The DEL is proposed as the process window enhancement technology for sub-110-nm technology. Features with sparse pitches are printed by a first step of dense pitch exposures and a second exposure with dummy features removed. The pattern decomposition strategy described is similar to that of subresolution assisting features (SRAF). So it is compatible with the traditional rule-based SRAF implementation methodology. By comparing the depth of focus (DOF) of the 110-nm lithography process between the single exposure and the double exposure, it is found that the DOF for marginal features is extended by using double-exposure methodology, and thus extends the capability of KrF exposure tools. Furthermore, the link between the overlay performance and the overlap of the second exposure's trim slots over the first exposure is studied. The results show that the overlay control is within the KrF scanner capability. As a further study, the proposed double-exposure methodology for the 90-nm lithography process is evaluated.
Due to the corner rounding effect in litho process, it is hard to make the wafer image as sharp as the
drawn layout near two-dimensional pattern in IC design1, 2. The inevitable gap between the design and
the wafer image make the two-dimensional pattern correction complex and sensitive to the OPC
correction recipe. However, there are lots of different two-dimensional patterns, for example, concave
corner, convex corner, jog, line-end and space-end. Especially for Metal layer, there are lots of jogs are
created by the rule-based OPC. So OPC recipe developers have to spend lots to efforts to handle
different two-dimensional fragment with their own experience.
In this paper, a general method is proposed to simplify the correction of two-dimensional structures.
The design is firstly smoothed and then simulation sites are move from the drawn layer to this new
layer. It means that the smoothed layer is used as OPC target instead of the drawn Manhattan pattern.
Using this method, the OPC recipe tuning becomes easier. In addition, the convergence of
two-dimensional pattern is also improved thus the runtime is reduced.
Design for Manufacturing (DFM) is being widely accepted as one of the keywords in cutting edge lithography and OPC
technologies. DFM solutions impact the design-to-silicon flow at various stages, often during different time-point in the
product life cycle, and often with both process equipments and metrology tools. As the design rule shrinks and mask
field size increases, tighter specifications are applied on non-critical layers, including thick implant resist typically with
thickness of 3.0um and above. Various functions, as Enhanced Global Alignment (EGA), Super Distortion Matching
(SDM), and Grid Compensation for Matching (GCM), are widely used to achieve improved overlay accuracy. However,
poor uniformity for CD and overlay was observed for thick resist implant layers. Systematic uncorrectable overlay
residue was observed from the overlay map. Cross-section analysis shows asymmetric resist profile existed, causing
inaccurate signal reading during the measurement. Although there are some recent researches focusing on CD-SEM
metrology of overlay residue, overlay tools in current foundries are mainly optical-based ones, which are limited by the
optical resolution. Instead of locally focusing on the manufacturing, an innovative methodology is proposed in this
paper, by applying the newly designed overlay marks to solve this manufacturing problem. From the comparison of
overlay performances between the proposed layout and the original design, it is shown that the taper asymmetry induced
errors are significantly reduced.
As the semiconductor industry scales down to 90nm and below, Model-Based OPC has become a standard practice to
compensate for optical proximity effects and process variations occurring when printing features below the exposure
wavelength. For parametric OPC models, it is assumed that the empirical data are accurate and the model parameter
space is sufficiently well sampled. In spite of advanced metrology tools, the measurement uncertainty for 1D small
critical dimensions and 2D patterns remains to be a challenge. Traditionally, the weight of SEM measurement points are
based on either statistical method such as standard deviations, or engineers' judgment, which is either time consuming or
individual-dependent. In this paper, the slope-integrated OPC model calibration methodology is proposed, which takes
into account the slope as a weighting indicator. The additional measurement objects per calibration structure are
economically feasible, as most metrology tool time is spent on addressing and auto-focusing. When we consider one
measurement point with both CD and slope measurements, the slightly increased time is tolerable for FAB, which
requires a short turn around time (TAT). By this approach, we can distinguish measurement points with low confidence
from those accurate ones. Furthermore, we check the fitting differences among equal-weighted data sheets, empiricalweighted
data sheets and slope-weighted data sheets, by using the same variable threshold model form. From the edge
placement error (EPE) of fitting results and the overlap between simulated contours and SEM images, it is found that the
proposed slope-integrated methodology results in a more accurate and stable model.
The effectacy of the OPC model depends greatly on test pattern data calibration that accurately captures mask and wafer
processing characteristics. The CD deviation caused by an off-center mask process can easily consume the majority of
the lithography process CD budget. Mask manufacturing variables such as write tools' resolution, etch process effects,
and pre-bias of the fractured data have great impacts on OPC model performance. As a result, wafer performance using
masks from different mask shops varies due to variations in the mask manufacturing process, even if the masks are
written with the same data set and use the same manufacturing specifications. A methodology for mask manufacturing
calibration is proposed in order to make an OPC model consistent between two mask manufacturing processes. The
methodology consists of two parts: mask manufacturing calibration and wafer-level OPC accuracy verification. The
mask manufacturing process and metrology are calibrated separately. The OPC model is built based on the database of
the first-party mask shop, and OPC verification is carried out by wafer data using the newly calibrated mask from the
second-party mask shop. By checking wafer performance of both OPC model matrix items and complicated 2D
structures, the conclusion can be drawn that different mask shops can share the same OPC model with rigorous mask
calibration. This methodology leads to lower engineering costs, shorter turn around time (TAT) and robust OPC
performance.
The number of tunable parameters increases dramatically as we push forward to the next node of hyper-NA immersion
lithography. It is very important to keep the lithographic process model calibration time under control, and its end result
insensitive to either the starting point in the parameter space or the noise in the measurement data. For minimizing the
least-squares error of a multivariate non-linear system, the industry standard is the Levenberg-Marquardt algorithm. We
describe a distributed computing technique that is natural to the algorithm, and easy to implement in a cluster of
computers. Applying this technique to calibrating lithographic process model, we can achieve robust optimization results
in nearly constant calibration time.
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