We have evaluated a unified mask pattern data format named "OASIS.MASK"1 and a unified job deck format
named "MALY"2 for mask tools as the input data formats of the inspection tool using the mask data and the photomask
produced with the 65nm design rule. The data conversion time and the data volume for the inspection data files were
evaluated by comparing with the results for using the native EB data and the native job deck data. The inspection speed
and the defect number of the inspection tool were also evaluated with the actual inspection tool. We have confirmed that
there is no large issue in applying OASIS.MASK and MALY to the input data formats of the inspection tool and they
can become the common intermediate format in our MDP flow. The detail of evaluation results will be mainly
introduced in this paper.
KEYWORDS: Photomasks, Inspection, Manufacturing, Design for manufacturing, Lithography, System on a chip, Optical proximity correction, Double patterning technology, Design for manufacturability, Semiconducting wafers
This is a report on a panel discussion organized in Photomask Japan 2008, where the challenges about "Mask
Complexities, Cost, and Cycle Time in 32-nm System LSI Generation" were addressed to have a look over the possible
solutions from the standpoints of chipmaker, commercial mask shop, DA tool vendor and equipments makers. The
wrap-up is as follows: Mask complexities justify the mask cost, while the acceptable increase rate of 32nm-mask cost
significantly differs between mask suppliers or users side. The efficiency progress by new tools or DFM has driven their
cycle-time reductions. Mask complexities and cost will be crucial issues prior to cycle time, and there seems to be linear
correlation between them. Controlling complexity and cycle time requires developing a mix of advanced technologies,
and especially for cost reduction, shot prices in writers and processing rates in inspection tools have been improved
remarkably by tool makers. In addition, activities of consortium in Japan (Mask D2I) are expected to enhance the total
optimization of mask design, writing and inspection. The cycle-time reduction potentially drives the lowering of mask
cost, and, on the other, the pattern complexities and tighter mask specifications get in the way to 32nm generation as well
as the nano-economics and market challenges. There are still many difficult problems in mask manufacturing now, and
we are sure to go ahead to overcome a 32nm hurdle with the advances of technologies and collaborations by not only
technologies but also finance.
Load of photomask manufacturing for the most advanced semiconductor devices is increasing due to the complexity of
mask layouts caused by highly accurate RET or OPC, tight specification for 2D/3D mask structures, and requirements of
quick deliveries. The mask cost becomes a concern of mask users especially in SoC businesses because the number of
masks required throughout the wafer process is almost the same for each product regardless of the variety in production
volume when a unified platform is applied to the designs. Shares of mask cost within total production cost cannot be
ignored especially in small volume SoC products.
DFM (design for manufacturing) is inevitable in a mask level as well as in a wafer level to solve the cost problem.
"Mask-DFM" is a method to decrease the burden of mask manufacturing and to improve the yield and quality of masks,
not only by modification of mask pattern layouts (design) but also all other things including utilization of designer's
intents.
We have developed our Mask-DFM system called "MiLE", that calculates mask-manufacturing workload through
layout analyses combining information of mask configuration, and visualizes the consequence of Mask-DFM efforts.
"MiLE (Mask manufacturIng Load Estimation)" calculates a relative index which represents the mask manufacturing
workload determined by factors of 1) EB writing, 2) defect inspection/repair, 3) materials and processes and 4)
specification. All the factors are computed before tape-outs for mask making in the system by the following methods.
To estimate EB writing time, we applied high-throughput simulator and counted the number of "shot", minimum figure
unit in EB writing, by using post-OPC layout data. Mask layout that caused troubles and extra load in mask
inspection or repair was specified from MRC (mask rule checking) of the same post-OPC data. Additional layout
analysis perceives designer's intents that are described in the layout data and these are reflected in the calculation of the
"MiLE" index. Finally, chip arrangement on a mask is retrieved from so-called electronic mask spec sheets to construct mask layouts.
"MiLE" notifies to designers the index of mask manufacturing workload that is caused by mask layout, while modification and adjustments of design or OPC are iterated to maximize device productivity in early design phases. Therefore, designers can judge and control the mask manufacturability, or mask cost by designs and additional intents
useful for mask making. In the production phases, our system releases useful information for mask manufacturing to a mask shop and decreases the mask manufacturing workload. In this paper, we report the outline and functions of MiLE system and the results of mask manufacturing workload calculation using post-OPC layout data.
Recently, mask design has been becoming more complex with the increase of data volume. Therefore, it requires more
functionality and portability in the mask specification and layout definition for the efficient data handling together with
industry standard. SEMI-P10 order format has universal layout definition for the all sorts of mask specifications. We
expect OASISTM (Open Artwork System Interchange Standard; SEMI standard P39) instead of conventional GDS-II to
come into wide use as a more compressive stream format for 45nm node and beyond. The OASIS format is suitable for
the enormous pattern file size and sub-nanometer design grid.
Although SEMI-P10 is convenient to achieve all of our requirements, its complete definition is very complicated and is
difficult to set up full parameters in the primary stage of mask design for production chips. In this work, we focused on
minimum syntax of the chip location information from portion of SEMI-P10. And we define P10-JOBDECK as a subset
of whole SEMI-P10 regulations. So, by use of P10-JOBDECK and OASIS data format, we have built up the new data
handling infrastructure such as data file transfer and pattern layout viewing for the high-end mask manufacturing.
In this system, the coordinates of P10-JOBDECK are described in 4X image with mirror inversion and tone reversal
parameters. We use 1X coordinates in P10-JOBDECK for the pattern data files because they are the dimensions familiar
to the designer, and the transformation for the mask shop is handled automatically. This style is effective for shortening
the data conversion time and preventing mishandling of data. We also developed the additional viewer functions of
HOTSCOPE® to confirm the pattern layout on the digital display.
It is possible to add mask DFM information (design information for mask manufacturability) by the extension to the full
SEMI-P10 syntax and by the use of built-in OASIS properties in the future.
In this paper, we will discuss the practical application of P10-JOBDECK and the performance results of HOTSCOPE.
Photomask pattern writer requires high-speed data processing that is conducted concurrently with the variable shaped
beam (VSB) writing. As input electron beam (EB) mask data, trapezoid data format is generally used for EB writing
because of the easier handling than polygon data format. Recent years, volume of photomask pattern data is growing
as the increase of pattern density that is caused by additional various subsidiary patterns of optical proximity correction
(OPC). OPC in design rules of 65nm and below is getting approximately 1.5 times more complex than that in the
former generation, which increases the photomask pattern data volume approximately 3 times larger.
VSB writing time is accurately estimated by counting the total number of "shots" which are primitive figures
generated in the data processing of EB writer from the trapezoid patterns in EB mask data. However, no feedback and
layout modification can be taken to LSI designs and OPC, even though problems regarding mask manufacturability such
as explosion of EB writing time is recognized after starting EB writing process.
We developed a simulator that estimates the number of "shots" in VSB EB writing by original shot division method
using design data GDSII instead of EB mask data. This simulator outputs total counts and density map of shots of EB
writing in photomask layout as well as chip layout in a short time using multi-processing. We can use this software as
a core function in our Mask-DFM solutions offering to LSI designers and CAD engineers in order to estimate mask
manufacturability before they finish mask data tape-out, and this work can reduce cost and improve TAT in mask manufacturing.
A novel mask structure for an alternating aperture phase shift mask (Alt-PSM) to cut mask cost is proposed. By a
mask with structure of an embedded attenuating phase shift mask (Atten-PSM), an Alt-PSM for an isolated line
formation can be well fabricated. Fine image quality is confirmed with optical image calculations. Moreover,
concept of this novel mask is proved by a preliminary experiment. In conclusion, this novel mask can replace
conventional Alt-PSM for logic devices, resulting in considerable cut of mask cost.
KEYWORDS: Design for manufacturing, Photomasks, Manufacturing, Design for manufacturability, Reticles, Standards development, Inspection, Optical proximity correction, System on a chip, Semiconductors
Design For Manufacturability Production Management (DFM-PM) Subcommittee has been started in succession to Reticle Management Subcommittee (RMS) in Semiconductor Manufacturing Technology Committee for Japan (SMTCJ) from 2005.
Our activity focuses on the SoC (System On Chip) Business, and it pursues the improvement of communication in manufacturing technique.
The first theme of activity is the investigation and examination of the new trends about production (manufacturer) technology and related information, and proposals of business solution.
The second theme is the standardization activity about manufacture technology and the cooperation with related semiconductors' organizations.
And the third theme is holding workshop and support for promotion and spread of the standardization technology throughout semiconductor companies.
We expand a range of scope from design technology to wafer pattern reliability and we will propose the competition domain, the collaboration area and the standardization technology on DFM. Furthermore, we will be able to make up a SoC business model as the 45nm node technology beyond manufacturing platform in cooperating with the design information and the production information by utilizing EDA technology.
Recent integrated circuit (IC) manufacturing processes require smaller critical dimension (CD) in order to facilitate the development of exposure tools with a higher numerical aperture (NA) and shorter wavelength. Consequently, the depth of focus (DOF) has considerably decreased, and the DOF currently required for 45-nm node devices is approximately 150 nm. Hence, the contribution of mask flatness to the total DOF increases. Inoue et al. systematically and precisely investigated the influence of mask flatness by using a free-standing plate and chucked plate interferometer. In this study, we fabricated several back side chrome (BSC) masks for focus monitoring, determined the flatness of these masks by an exposure experiment, and compared the flatness with that directly determined by using a free-standing plate interferometer. Thus, we verified the possibility of predicting the mask flatness component on an image plane by using the mask flatness data obtained using the interferometer.
KEYWORDS: Photomasks, Design for manufacturing, Lithography, Semiconductors, System on a chip, Maskless lithography, Optical proximity correction, Semiconducting wafers, Polarization, Design for manufacturability
Semiconductor devices are making important role in our life. Many semiconductor chips will be used to every thing, and we will receive the various services anywhere anytime through a digital network. There are so many applications using semiconductor products that support such a ubiquitous era, and it is expected that mobile, automobile and PC/AV applications will have the great growth from now on.
In this paper, we describe the lithography technology trend and requirements for mask technology from the view point of SOC and FLASH memory trend. From the device development trend, it is expected that FLASH memory become driving force of lithography technology. To realize hp45nm node and beyond, the installation of hyper-NA ArF-immersion tools with low-k1 technique is the key issue. With this, DFM (Design For Manufacturability) is the key technology and a continuous approach of systematic DFM technique is important in order to reduce chip cost. Also, Mask DFM is needed to realize cost-effective low-k1 process and it drives reasonable mask cost and TAT. In order to reduce mask cost in device development and small volume production, we expect greatly that maskless lithography (ML2) become a leading tool in lithography.
Application of long wavelength in lithography process has a great benefit for cost of ownerships (COO) of semiconductor manufacturers, however there’s a trade off of reducing process margins due to the low k1 condition, and all the efforts in order to obtain large process windows on wafer connect directly to chip production management. In this paper, the authors used 248 nm wavelength lithography with alternating phase shift mask (alt-PSM) to develop 90 nm line and space patterns in 90 nm half pitch on wafer, and thoroughly investigated printability of defects and defect-repairs on alt-PSM. Sensitivity analysis of photomask defect inspection tools was implemented and it showed that existing inspection tools satisfied requirements for detection of chrome (Cr) and quartz (Qz) defects, which had impacts on wafer. Printability of Cr and Qz defect repairs was evaluated focusing on through-defocus behavior, and conditions of defect repair were optimized to reduce variation of critical dimension (CD) on wafer. The repair conditions were also optimized by estimation of overlaps of process windows of defect-repaired area on that of non-defective references. Process windows were analyzed based on both wafer and aerial image measurements. In the last section of this paper, we discussed managing process windows of defect repairs by controls of biases and Qz heights as parameters on defect-repaired areas and suggested that total topography control around defective area was required in addition to the prospected parameters in order to maximize process margins.
We have developed a resist-shade mask (R-mask) technology applicable for small-volume production. The R-mask uses a novel resist as a shading material instead of chromium (Cr), and it exhibits sufficient durability against KrF exposure for ASIC and pilot line applications. Because the R-mask does not require a Cr etching process, it can reduce mask costs and improve critical dimension (CD) uniformity. A defect inspection technique for R-masks has also been investigated, and no defects were observed on a wafer for several R-masks used for device fabrication. The part of the R-mask making contact in exposure tools was carefully designed to not retain resist material so as to avoid particle contamination. We applied several R-masks to form wiring layers for 0.25-um and 0.18-um logic devices and confirmed that there were no differences in process margin and product yield between the R-masks and conventional Cr masks.
We have also developed the partial R-mask, which consists of both conventional Cr mask and R-mask areas. The partial R-mask is very effective for customizing semiconductor chips. The R-mask area is applied only to customized circuit areas or certain wiring patterns to adjust circuit characteristics, whereas the common circuit area is delineated by the Cr pattern. The R-mask can be also used to customize attenuated phase-shifting masks, and to make unnecessary hole patterns opaque in prepared hole arrays.
The R-mask is a very promising technology for reducing mask costs and improving the turn-around time (TAT) of masks, because of its simple manufacturing process and reworkable capability.
Increase of cost and long turn-around-time (TAT) are becoming hot topics for advanced photomasks. Especially, in the small volume production such as SoC and pilot production, the mask cost and TAT are becoming an important issue for the semiconductor industry. To get rid of these issues, we propose the R-mask (resist shade mask) concept, and in this paper, we will focus on the fabrication techniques of the R-mask. The essential of the R-mask is the simplification of mask fabrication and inspection process. A newly developed e-beam resist, which is able to shield the KrF light, is used as the mask pattern material instead of the chrome. Pellicle is mounted immediately after the mature development process, so that defect density could be reduced. Furthermore, the R-mask concept omits mask cleaning and repair process. We evaluated the newly developed e-beam resist from the standpoint of applicability to mask manufacturing, and we successfully made an R-mask for 180nm metal layer pattern with the new resist. In this paper the process performance of resist is reported.
In recent years, Quick-TAT (Turn-Around Time) in preparing masks is very important factor together with the complexity and cost in mask development and manufacturing in higher-end devices. Especially in the development phase of customer-driven devices such as SOC, MCU and so on, QTAT role of mask supply might get a larger weight in LSI business. However, overhead in workflow, system and burden of mask users (designer, etc) in mask making are significant, not to mention the increase of OPC processing time and DA cost. For responding to the efficient and precipitous manufacturing requirement even for complicated leading-edge devices, we should focus on the optimization of workflow system minimization of mask-work resources in users (designer, etc.). Therefore, new Renesas Integrated Mask Operation System (RIMOS) has been developed as making masks “Everywhen you want” supporting five key functions as follows: (1) Simple interface to input mask-making parameters on Web-based integrated system (2) Hierarchical specification system of high maintainability and capability for SEMI-P10 format (3) Easy operation to instruct build-in specification for manufacturing such as complicated CD inspection (4) Bi-directional synchronization between mask-shop and wafer-fabs MES supporting the flexible multi-pass supply of masks (5) On-line quality reporting for mask-SPC monitoring supporting. This paper shows architecture of the new system 'RIMOS' and the estimate of TAT reduction in workflow.
The new repair of the clear defects on the half-tone PSM (EAPSM) was proposed. The Ga (gallium) ions were implanted by the FIB on the area adjacent to the carbon films formed on the clear defects. The Ga ion implanted area on the SiO2 substrate showed the semi-transparency at the KrF and ArF wavelengths. The lithography simulations of the layouts designed for the defect-repaired area endorsed the concept of the new repair. The Ga ion implantation was optimized to the new repair by using the AIMS and AFM measurements for the transmittance and etched depth of the SiO2 surface. The authors applied this method to the clear defects programmed on the KrF and ArF EAPSMs. The AIMS analysis showed that the deviation of the CD (critical dimension) of the defect-repaired regions on the wafer was within +/-5% to the non-defective reference at every defocused point. The new repair moderated the specification of the edge placement accuracy of the FIB processing compared to the conventional carbon film deposition.
The critical dimensions (CD) change by the process delay is the most critical issue to apply the chemically amplified resists (CAR) for photomask fabrication. In the photomask fabrication processes, the resist should have both post coating delay (PCD) and post exposure delay (PED) stability, while keeping higher sensitivity. To achieve this requirement, overcoat process has been examined for the purpose of CD stabilization in CAR process for photomask manufacture. The material, which consists of hydrophobic polymer and PAG, was used for the overcoat in this study. Consequently, it has become clear that pattern formations have been possible without unnecessary thickness loss. Moreover, it has been proved that the overcoat shows the effect of controlling CD change and improvement of CD uniformity. From these results, it is thought that the overcoat process is promising for the size stabilization in photomask manufacture for devices less than 90 nm.
As 90 nm devices enter into the pre-production phase, the quality assurance strategy of photomasks for those devices must be well established with the proper cost and turn-around-time in mind. Such devices will be manufactured with a state-of-the-art photolithography systems equipped with 193nm actinic light sources. Photomasks for these devices are being produced with the most advanced equipment, material and processing technologies and yet, quality assurance still remains an issue for volume production. These issues include defect classification and disposition due to the insufficient resolution of the defect inspection system, uncertainty of the impact the defects have on the printed feature as well as inconsistencies of classical defect specifications as applied in the sub-wavelength era. To overcome these issues, the authors propose a new strategy to assess photomask quality by checking the CD variation on wafer (defect printability) using aerial image simulation. This method of simulation-based mask qualification uses aerial image defect simulation in combination with a high resolution optical review system with shorter review wavelength (248nm) and smaller pixel size (22.5nm)- combining the defect inspection system with a longer inspection wavelength (365nm) and larger pixel size (150nm). This paper discusses a new strategy on mask quality assurance with several experimental results that proves the applicability for enabling 90nm technology nodes. Combining high-resolution optical images captured by DUV measurement tool with Virtual Stepper System has achieved better accuracy for 0.72um contact holes on ArF Att.PSM. However, we need further investigation for precise prediction of CD variation caused by defects on 0.4um line/space patterns on ArF Att.PSM. This paper also discusses future work to make the strategy production-worthy.
The KrF12% tri-tone PSM (phase shift mask) was designed with the programmed defects on the chrome (Cr) and phase shift (PS) layers. From the lithography simulation, the PS defects, generated on the PS layer, were estimated to fluctuate the CD of the contact holes on the wafer more than the defects in the same size on the conventional EAPSM (half-tone PSM). The printability of the PS defects and Cr defects on the contact holes were investigated by the print-test on the wafer. The Cr residues on the PS layer slightly changed the CD of the contact holes on the wafer. The PS defects showed the great influence to the CD variation of the contact holes. The light calibration of the defect inspection was optimized to detect the PS and Cr defects. For the detection of the PS defects in the die-to-die inspection mode, the UV inspection system SLFX7 showed the high performance with the PS/SiO2 calibration, in which the boundary of the PS layer and SiO2 substrate was used as the light calibration point. The SLFX7 also available to detect the Cr defects in the die-to-die mode. For the die-to-database mode to detect the Cr defect, the KLA351, the visible light inspection system, was available by the Cr/PS calibration. The sensitivity of the SLFX7 and KLA351 was adequate for the Cr defects, however, that was not enough to the specification of the PS defects estimated from the print-test. The sensitivity of the SLFX7 showed a slight difference between the tri-tone and binary layout in the specific defect types.
The critical dimensions (CD) change by the process delay is the most critical issue to use the chemically amplified resists (CAR) for photomask fabrication. In the photo-mask fabrication processes, the resist should have both post coating delay (PCD) and post exposure delay (PED) stability, while keeping higher sensitivity. To achieve this requirement, overcoat process has been examined for the purpose of CD stabilization in CAR process for photomask manufacture. The material, which consists of hydrophobic polymer and photo acid generator (PAG), was used for the overcoat in this study. It has been proved that the overcoat shows the effect of controlling CD change, and applying the overcoat does not generate a fatal number of defects and pinholes. From these results, it is thought that the overcoat process is promising for the size stabilization in photomask manufacture for 100 nm devices.
We are focusing on a high-performance cleaning process with minimum use of chemicals. For the substitution of chemicals, the refined cleaning tools and process have been developed, which use the high-concentration ozonic together with hydrogen water. To optimize a cleaning process, we have evaluated the removal and decomposition efficiency of organic compounds on the mask surface, the optical degradation of Cr and Suicide materials and so on. In conclusion, the substitution of sulfuric acid, ammonia and other chemicals is available for practical cleaning process by combining their functional cleaning steps. Especially in the ArF generation, this cleaning technique was found to be promising for the reduction of optical-damage and chemical residues for mask patterns and as well as high-efficiency particle removal.
In this paper, we focused on the refined cleaning process with minium use of chemicals. We developed a cleaning tools and process using high-concentration ozonic water generated by the high-efficiency ozonizing apparatus (OW00345, Mitsubishi Electric Corp. Industrial Systems), as chemicals substitution. To optimize a cleaning process, we have evaluated the removal and decomposition efficiency of organic compounds on the mask surface, the optical degradation of Cr and Siliside materials and so on.
Attenuated phase-shifting mask with a single-layer absorptive shifter of CrO, CrON, MoSiO or MoSiON films has been developed. The optical parameter of these films can be controlled by the condition of sputtering deposition. These films satisfy the shifter requirements, both the 180-degrees phase shift and the transmittance between 5 and 20% for i-line. MoSiO and MoSiON films also satisfy the requirement for KrF excimer laser light. Conventional mask processes, such as etching, cleaning, defect inspection and defect repair, can be used for the mask fabrication. Defect-free masks for hole layers of 64 M-bit DRAM are obtained. Using this mask, the focus depth of 0.35-micrometers hole is improved from 0.6 micrometers to 1.5 micrometers for i-line lithography. The printing of 0.2-micrometers hole patterns is achieved by the combination of this mask and KrF excimer laser lithography.
In this new process for phase-shifting mask fabrication, molybdenum silicide (MoSi) is used as an optical shield layer and spin-on glass (SOG) as a phase-shifter layer. Chromium is employed as an etch-stopper during SOG etching. Cr etch-stopper will be removed at the end of tiie process, therefore all optical problems related to an etch-stopper are avoided. This Cr etch-stopper is also useful in inspection and repair of shifter remaining defects. At first, we will describe the fabrication process including the shifter-defect inspection and repair. Secondary, we will discuss the phase-shifting mask accuracy and its influence to the printed resist pattern when using the alternating type phase-shifting mask. Lastly,we will mention the application result of development of lithography for 64Mbit DRAM using this process.
The pattern data representing ULSI photolithography layers continues to grow exponentially when viewed at the image plane. Data derivation, verification, conversion, and movement have resulted in significant logistical problems and reticle production bottlenecks even with current device densities and reticle manufacturing technologies. With the advent of phase shifting reticle manufacturing and even more dense ULSI devices, database image generation for reticle defect inspection becomes an even more serious issue. Examination of 64 MBit pattern characteristics show that total figure counts per layer approach 1 billion figures per layer. Phase shifting structures increase figure counts per layer to over 1 billion figures. Defect sensitivities of 0.40 micrometers for chrome defects and 0.30 micrometers for phase shift defects are required for 64 MBit reticle inspection. Single die inspection area exceeds 5000 mm2 and die pixel counts are over 1011 pixels. Current reticle inspection database image generation technology requires ten hours per inspection pass. Data load times exceed one hour and data conversion to the inspection format exceeds ten hours. Total reticle inspection time in the manufacturing environment may approach 40 hours. A novel pattern generator architecture allowing 64 MBit reticle inspection in one hour is proposed. The NPG architecture includes a new data format, an integrated data conversion package, and a high resolution, high speed image generator. NPG data conversion performance is analyzed and 782 million figure 64 MBit data conversions are performed in less than one minute. Resulting file sizes are one million bytes. The NPG data format is shown to allow increased edge placement resolution to support increased inspection sensitivity. A method for simultaneously generating chrome and phase shift images is presented.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.