Dr. Katja Viatkina Profile

Dr. Katja Viatkina

Research Engineer at ASML Netherlands BV

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Publications (5)

Proceedings Article | 20 March 2019 Presentation + Paper

Scanner and etch co-optimized corrections for better overlay and CD control

Ik-Hyun Jeong , Seung-Woo Koo, Hyun-Sok Kim, Jae-Wuk Ju, Young-Sik Kim, Yong-Tae Cho, Heung-Joo Kim, Katja Viatkina, Tom van Hemert, Ruud de Wit, David Deckers, Owen Chen, Nang-Lyeom Oh, Marcus Musselman, Marcus Carbery, Ssuwei Chen, Lucian Schmidt, Heidi Kwon, Jae Gyoo Lee

Proceedings Volume 10963, 1096308 (2019) https://doi.org/10.1117/12.2516578

KEYWORDS: Etching, Overlay metrology, Scanners, Semiconducting wafers, Metrology, Critical dimension metrology, Lithography, Plasma, Process control, Optical lithography

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Proceedings Article | 24 March 2017 Paper

Reducing the impact of etch-induced pattern shift on overlay by using lithography and etch tool corrections

Michael Kubis, Rich Wise, Charlotte Chahine, Katja Viatkina, Samee Ur-Rehman, Geert Simons, Mircea Dusa, David Hellin, Daniel Sobieski, Wenzhe Zhang, Christiane Jehoul, Patrick Jaenen, Philippe Leray

Proceedings Volume 10147, 101470H (2017) https://doi.org/10.1117/12.2260000

KEYWORDS: Etching, Scanners, Semiconducting wafers, Optical lithography, Overlay metrology, Lithography, Immersion lithography, Metrology, Atomic force microscopy, Ions, Critical dimension metrology

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With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter. For the 5-nm node and beyond, on-product overlay below 2.5nm is required. Achieving such performance levels will not only need optimization of scanner performance but a holistic tuning of all process steps. In previous work, it has been shown that process-induced pattern asymmetry has significant impact on overlay performance at wafer edge and can be partially compensated by applying high-order scanner corrections or optimizing metrology targets. Today, we present the reduction of process-induced pattern asymmetry in a tunable etch system and demonstrate the related on-product overlay improvement combined with scanner corrections.

In our work we utilize etch tools (Lam Kiyo® conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a state-of-the-art 1.35 NA immersion scanner (NXT:1970Ci).

The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar® S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm.

Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.

Proceedings Article | 24 March 2017 Presentation + Paper

Integrated approach to improving local CD uniformity in EUV patterning

Andrew Liang, Jan Hermans, Timothy Tran, Katja Viatkina, Chen-Wei Liang, Brandon Ward, Steven Chuang, Jengyi Yu, Greg Harm, Jelle Vandereyken, David Rio, Michael Kubis, Samantha Tan, Mircea Dusa, Akhil Singhal, Bart van Schravendijk, Girish Dixit, Nader Shamma, Rich Wise, Sirish Reddy

Proceedings Volume 10143, 1014319 (2017) https://doi.org/10.1117/12.2258192

KEYWORDS: Extreme ultraviolet lithography, Etching, Extreme ultraviolet, Lithography, High volume manufacturing, Stochastic processes, Plasma etching, Reactive ion etching, Plasma enhanced chemical vapor deposition, Focus stacking software, Photomasks

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Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies.

Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.

Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Proceedings Article | 15 March 2016 Paper

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

Michael Kubis, Rich Wise, Liesbeth Reijnen, Katja Viatkina, Patrick Jaenen, Melisa Luca, Guillaume Mernier, Charlotte Chahine, David Hellin, Benjamin Kam, Daniel Sobieski, Johan Vertommen, Jan Mulkens, Mircea Dusa, Girish Dixit, Nader Shamma, Philippe Leray

Proceedings Volume 9780, 978007 (2016) https://doi.org/10.1117/12.2220591

KEYWORDS: Critical dimension metrology, Etching, Lithography, Optical lithography, Scanners, Process control, Logic, Scatterometry, Photomasks, Plasma etching, Metrology

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Proceedings Article | 20 March 2015 Paper

Influence of etch process on contact hole local critical dimension uniformity in extreme-ultraviolet lithography

Gian Lorusso, Ming Mao, Liesbeth Reijnen, Katja Viatkina, Roel Knops, Gijsbert Rispens, Timon Fliervoet

Proceedings Volume 9425, 94250K (2015) https://doi.org/10.1117/12.2085722

KEYWORDS: Etching, Semiconducting wafers, Scanning electron microscopy, Oxides, Photomasks, Wet etching, Extreme ultraviolet lithography, Polymers, Metrology, Critical dimension metrology

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Contact Hole (CH) Local Critical Dimension Uniformity (LCDU) has a direct impact on device performance. As a consequence, being able to understand and quantifying the different LCDU contributors and the way they evolve during the various process steps is critical. In this work the impact of etch process on LCDU for different resists and stacks is investigated on ASML NXE:3100 and NXE:3300. LCDU is decomposed into shot noise, mask, and metrology components. The design of the experiment is optimized to minimize the decomposition error. CD and LCDU are monitored and found to be stable.

We observed that the net effect of the etch process is to improve LCDU, although the final LCDU is both stack- and resist-dependent. Different resists demonstrate the same LCDU improvement, so that the LCDU after etch will depend on the initial resist performance. Using a stack different from the one used to set up the etch process can undermine the LCDU improvement.

The impact of the various etch steps is investigated in order to identify the physical mechanisms responsible for the LCDU improvement through etch. Both top-down and cross section Scanning Electron Microscopy (SEM) are used. The step-by-step analysis of the etch process showed that the main LCDU improvement is achieved during oxide etch, while the other process steps are either ineffective or detrimental in terms of LCDU. The main cause of the LCDU improvement is then attributed to the polymerization of the CH surface happening during the oxide etch.

Finally, the LCDU improvement caused by the etch process is investigated as a function of the initial LCDU after litho in a relatively broad range (2-15nm). The ratio between LCDU after litho over LCDU after etch is investigated as a function of the initial LCDU after litho for two different resists. The results indicate that the impact of etch on LCDU is characterized by a single curve, specific to the etch process in use and independent of the resist type. In addition, we observe that the percentage LCDU improvement is constant above a certain threshold, in agreement with the throughpitch results.

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