HAL, the disembodied robotic voice ever present in the Arthur C. Clark movie 2001, A Space Odyssey, is the archetype for artificial intelligence. What will it take to achieve HAL? Trillions of highly interconnected arithmetic units in very close proximity is mandatory. Moore's Law and 3D SILICON will get that part done. Linguistic articulation of experience and direction of action is the other missing piece. The human version's neural circuits are basically just multiply-and-add template matchers and yet verbalization of experience is the apparently automatic result. We call this recognition based logic and by embedding it in a properly interconnected processor network, the capabilities of HAL will be achieved.
A commercial version of the 3D Artificial Neural Network has been developed under a collaborative effort between JPL and Irvine Sensors, sponsored by BMDO and the U.S. Air Force. It is capable of continuous trillion eight bit multiply and add operations per second while consuming under ten watts. Its architecture, input-output characteristics, and performance data will be presented.
Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.
A variety of projects have been recently completed or are underway that utilize 3D architectures to achieve major enhancements of focal plane array signal processing capabilities. Progress will be presented in the areas of non-uniformity correction analog-to- digital conversion, spatial and temporal filtering, foveal vision, event-driven multiplexing, and neural pattern recognition. This progress is the result of on-going collaborative and individual efforts under direction of the authors.
3D silicon technology has been under development since 1980, primarily aimed at on-focal- plane signal processing to solve a variety of military sensor systems problems. The thrust has been to bring more and more parallel analog and digital processing into the closest possible proximity to the detector array. At this time on-focal-plane functionality includes preamplification, spatial and temporal matched filtering, nonuniformity correction, neural networks, analog-digital conversion, digital logic, and digital memory. Historically, a custom- built specialty technology constrained by cost in its applicability, 3D silicon has undergone a dual-use conversion to include high-volume, low-cost commercial computer electronics. 3D silicon is on the way to becoming the lowest-cost-per-gate technology available and, because of this, sensor system design and performance will be revolutionized.
3-D focal plane array read-out structures offer the means for a fully interconnected, many level neural network with the potential for biological recognition capabilities. In this, the first of a two part paper, the 3DANN concept is presented and described. The second part discusses and compares the hardware implementation with more conventional approaches.
This paper presents conceptual designs for high density packaging of parallel processing systems. The systems fall into two categories: global memory systems where many processors are packaged into a stack, and distributed memory systems where a single processor and many memory chips are packaged into a stack. Thermal behavior and performance are discussed.
The marriage of superconducting electronics with Z-plane FPA readout structures offer the potential for high speed, low power parallel digital processing on-focal plane. This paper reports on some early research into this marriage of two technologies conducted by Irvine Sensors Corporation (ISC) and TRW. Progress is reviewed for both low and high temperature superconducting technologies.
3-D focal plane array readout structures offer the means for a fully interconnected, many level neural network with the potential for biological recognition capabilities. In this, the second of a two part paper, the 3DANN hardware design is discussed and its neural processing capabilities compared with other technologies.
KEYWORDS: Sensors, Signal processing, Neural networks, Detector arrays, Information operations, Artificial neural networks, Analog electronics, Filtering (signal processing), Signal detection, Digital signal processing
Neural networks offer the potential for a quantum leap in the capabilities of imaging sensor systems. The critical
neural network implementation factors are: weighted interconnect between all detector outputs; parallel, linear processing
of each detector output; fan-out to multiple (thousands) processing nodes per detector output and the ability to independently
change interconnect weights and processor node connections within the detector integration times. For a 128 x 128 pixel
detector array, the number of desirable interconnects could be as high as iO per second, compared to the approximately
iO rates achieved presently with off-focal plane digital processors. Irvine Sensors Corporation (ISC) has conceived a new
way of interconnecting 3-D focal plane readout modules and of laying out their component integrated circuits that appears
to fulfill the very high interconnect rate requirements. This concept is described and mterconnectivity and other performance
attributes are discussed.
Miss distance performance has generally required a significant simulation effort. Missile simulation
models generally require substantial modification to adapt them to a new system concept or to make
major changes within the interceptor design. By conducting a sensitivity analysis, an alternate approach
is presented to assist the analysis of the the miss and establishing the system level requirements.
The analysis section of this paper analyzes each of the three miss components aimpoint determination,
measurement accuracy, and interceptor dynamic response. Observation and sample calculations are
presented for a maneuvering and a non-maneuvering target. Once the miss requirement has been
analytically determined as a function P, then the analytical process can be worked backwards to
determine the range and range rate uncertainty requirement at handover, or if at the start of end
game engagement, the total angular accuracy (in a r.s.s sense) of the system and required data rate
may be determined.
The usefulness of Z-plane technology to GEO instrumentation with regard to data fidelity, data compaction, and parallel processing is discussed. The application of Z-plane technology to imaging spectrometers and advanced lightning mappers is addressed. Desirable design characteristics for Z-plane signal processing are given.
KEYWORDS: Sensors, Satellites, Space operations, Surveillance, Staring arrays, Digital signal processing, Target detection, Defense and security, Telecommunications, Infrared sensors
This paper describes the key technology, onboard processing, and integration of a space reconnaissance platform consisting of a small smart satellite (Smartsat) designed for compatibility with the launch envelope of a Pegasus class vehicle. Because the platform is designed to the Pegasus class baseline, the operations scenario can use a launch-on-demand concept that provides inherent advantages for tactical force commanders that are not achievable in today's environment. In a very significant departure from traditional designs, Smartsat houses sufficient onboard digital processing so that usable data can be downlinked directly to the forward-located force commanders. This feature minimizes the requirement for high bandwidth data links to the ground and the consequent dependence on large, vulnerable central processing ground stations to produce and distribute usable data for the decision makers. An example of how Smartsat might be applied to tactical air defense is given.
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