We present a fully integrated photonic chip spectrometer for near-infrared tunable diode laser absorption spectroscopy of methane (CH4). The integrated photonic sensor incorporates a heterogeneously integrated III-V laser/detector chip coupled to a silicon external cavity for broadband tuning, and a long waveguide element (>20 cm) for ambient methane sensing. An on-chip sealed CH4 reference cell is utilized for in-situ wavelength calibration of the external cavity, and a real-time wavelength compensation method for laser calibration is described and demonstrated. The resulting signal is guided back to the III-V photodiodes for spectral signal readout using a custom-designed acquisition board, remotely controlled and operated by a Raspberry Pi unit. Component-level testing of the waveguide sensitivity, external cavity laser, and reference cell is demonstrated. Full-stack testing of the integrated sensor chip yields sub-100 ppmv∙Hz-1/2 sensitivity, and spectral density analysis demonstrates our integrated chip sensor to have a fundamental performance within an order of magnitude of commercially available fiber-pigtailed DFB laser units. We envision our integrated photonic chip sensors to provide disruptive capability in SWaP-C (size, weight, power, and cost) limited applications, and we describe an achievable short-term pathway towards sensitivity enhancement to near-10 ppmv levels.
We present a chip-scale spectroscopic methane sensor, incorporating a tunable laser, sensor waveguides, and methane reference cell, assembled as a compact silicon photonic integrated circuit. The sensor incorporates an InP-based semiconductor optical amplifier/photodetector array, flip-chip soldered onto a silicon photonic substrate using highprecision waveguide-to-waveguide interfaces. The InP chip provides gain for a hybrid external cavity laser operating at 1650 nm. The sensor features a 20-cm-long TM-mode evanescent-field waveguide as the sensing element and is compatible with high-volume wafer-scale silicon photonics manufacturing and assembly processes. This sensor can be an enabling platform for economical methane and more general distributed environmental trace-gas monitoring.
We present a portable optical spectrometer for fugitive emissions monitoring of methane (CH4). The sensor operation is based on tunable diode laser absorption spectroscopy (TDLAS), using a 5 cm open path design, and targets the 2ν3 R(4) CH4 transition at 6057.1 cm-1 (1651 nm) to avoid cross-talk with common interfering atmospheric constituents. Sensitivity analysis indicates a normalized precision of 2.0 ppmv·Hz-1/2, corresponding to a noise-equivalent absorbance (NEA) of 4.4×10-6 Hz-1/2 and minimum detectible absorption (MDA) coefficient of αmin = 8.8×10-7 cm-1·Hz-1/2. Our TDLAS sensor is deployed at the Methane Emissions Technology Evaluation Center (METEC) at Colorado State University (CSU) for initial demonstration of single-sensor based source localization and quantification of CH4 fugitive emissions. The TDLAS sensor is concurrently deployed with a customized chemi-resistive metal-oxide (MOX) sensor for accuracy benchmarking, demonstrating good visual correlation of the concentration time-series. Initial angle-ofarrival (AOA) results will be shown, and development towards source magnitude estimation will be described.
Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.
The LER and LWR of subtractively patterned Si and SiN waveguides was calculated after each step in the process. It was found for Si waveguides that adjusting the ratio of CF4:CHF3 during the hard mask open step produced reductions in LER of 26 and 43% from the initial lithography for isolated waveguides patterned with partial and full etches, respectively. However for final LER values of 3.0 and 2.5 nm on fully etched Si waveguides, the corresponding optical loss measurements were indistinguishable. For SiN waveguides, introduction of C4H9F to the conventional CF4/CHF3 measurement was able to reduce the mask height budget by a factor of 5, while reducing LER from the initial lithography by 26%.
We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a “More-than- Moore” technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.
We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in
unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process –
the same process used to make many commercially available microprocessors including the IBM Power7 and Sony
Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available,
which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices
with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the
constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to
create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby
eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline
silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the
full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting
electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of
a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically
integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic
transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of
photonics into the microprocessor.
Silicon is considered a promising platform for photonic integrated circuits as they can be fabricated in state-of-the-art
electronics foundaries with integrated CMOS electronics. While much of the existing work on CMOS photonics has
used directional couplers for power splitting, multimode interference (MMI) devices may have relaxed fabrication
requirements and smaller footprints, potentially energy efficient designs. They have already been used as 1x2 splitters,
2x1 combiners in Quadrature Phase Shift Keying modulators, and 3-dB couplers among others. In this work, 3-dB,
butterfly and cross MMI couplers are realized on bulk CMOS technology. Footprints from around 40um2 to 200 um2 are obtained. MMI tolerances to manufacturing process and bandwidth are analyzed and tested showing the robustness of the MMI devices.
Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI
CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model,
integration was accomplished on multi-project wafers that were shared by standard electronic
customers without requiring in-foundry process changes. Simple die or wafer-level post-processing
has enabled low-loss waveguides by the removal of the substrate within photonic regions. The
custom-process model of the DRAM industry instead enabled optimization of the photonic device
fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline
silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS
process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic
transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also
demonstrated within this process [1]. The constraints of zero-change integration have limited
achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS
processes [2]. Custom polysilicon deposition and processing conditions available for DRAM
integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration
within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required
process features, device design guidelines and integration methodology tradeoffs will be presented.
Relevant device metrics of area and energy efficiency as well as achievable photonic device
performance will be presented within the context of monolithic front-end integration within state-ofthe-
art electronics processes. Applications of this research towards the implementation of a
computer system utilizing photonic interconnect for core-to-memory communication will also be
discussed.
Sampling rates of high-performance electronic analog-to-digital converters (ADC) are fundamentally limited by the timing jitter of the electronic clock. This limit is overcome in photonic ADC's by taking advantage of the ultra-low timing jitter of femtosecond lasers. We have developed designs and strategies for a photonic ADC that is capable of 40 GSa/s at a resolution of 8 bits. This system requires a femtosecond laser with a repetition rate of 2 GHz and timing jitter less than 20 fs. In addition to a femtosecond laser this system calls for the integration of a number of photonic components including: a broadband modulator, optical filter banks, and photodetectors. Using silicon-on-insulator (SOI) as the platform we have fabricated these individual components. The silicon optical modulator is based on a Mach-Zehnder interferometer architecture and achieves a VπL of 2 Vcm. The filter banks comprise 40 second-order microring-resonator filters with a channel spacing of 80 GHz. For the photodetectors we are exploring ion-bombarded silicon waveguide detectors and germanium films epitaxially grown on silicon utilizing a process that minimizes the defect density.
Photonic Analog-to-Digital Conversion (ADC) has a long history. The premise is that the superior noise performance of
femtosecond lasers working at optical frequencies enables us to overcome the bottleneck set by jitter and bandwidth of
electronic systems and components. We discuss and demonstrate strategies and devices that enable the implementation
of photonic ADC systems with emerging electronic-photonic integrated circuits based on silicon photonics. Devices
include 2-GHz repetition rate low noise femtosecond fiber lasers, Si-Modulators with up to 20 GHz modulation speed,
20 channel SiN-filter banks, and Ge-photodetectors. Results towards a 40GSa/sec sampling system with 8bits resolution
are presented.
Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse
trains that show jitter on the level of a few femtoseconds over tens of milliseconds and over seconds if referenced to
atomic frequency standards. These low jitter sources can be used to perform opto-electronic analog to digital conversion
that overcomes the bottleneck set by electronic jitter when using purely electronic sampling circuits and techniques.
Electronic Photonic Integrated Circuits (EPICs) may enable in the near future to integrate such an opto-electronic
analog-to-digital converters (ADCs) completely. This presentation will give an overview of integrated optical devices
such as low jitter lasers, electro-optical modulators, Si-based filter banks, and high-speed Si-photodetectors that are
compatible with standard CMOS processing and which are necessary for the implementation of EPIC-chips for advanced
opto-electronic ADCs.
Progress in developing high speed ADC's occurs rather slowly - at a resolution increase of 1.8 bits per decade. This slow progress is mostly caused by the inherent jitter in electronic sampling - currently on the order of 250 femtoseconds in the most advanced CMOS circuitry. Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse trains that show jitter on the level of a few femtoseconds over the time spans of typical sampling windows and can be made even smaller. The MIT-GHOST (GigaHertz High Resolution Optical Sampling Technology) Project funded under DARPA's Electronic Photonic Integrated Circuit (EPIC) Program is trying to harness the low noise properties of femtosecond laser sources to overcome the electronic bottleneck inherently present in pure electronic sampling systems. Within this program researchers from MIT Lincoln Laboratory and MIT Campus develop integrated optical components and optically enhanced electronic sampling circuits that enable the fabrication of an electronic-photonic A/D converter chip that surpasses currently available technology in speed and resolution and opens up a technology development roadmap for ADC's. This talk will give an overview on the planned activities within this program and the current status on some key devices such as wavelength-tunable filter banks, high-speed modulators, Ge photodetectors, miniature femtosecond-pulse lasers and advanced sampling techniques that are compatible with standard CMOS processing.
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