OPC models have become critical in the manufacturing of integrated circuits (ICs) by allowing correction of complex designs, as we approach the physical limits of scaling in IC chip design. The accuracy of these models depends upon the ability of the calibration set to sufficiently cover the design space, and be manageable enough to address metrology constraints. We show that the proposed method provides results of at least similar quality, in some cases superior quality compared to both the traditional method and sample plan sets of higher size. The main advantage of our method over the existing ones is that it generates a calibration set much faster, considering a large initial set and even more importantly, by automatically selecting its minimum optimal size.
It is desired to reduce the time required to produce metrology data for calibration of Optical Proximity Correction (OPC) models and also maintain or improve the quality of the data collected with regard to how well that data represents the types of patterns that occur in real circuit designs. Previous work based on clustering in geometry and/or image parameter space has shown some benefit over strictly manual or intuitive selection, but leads to arbitrary pattern exclusion or selection which may not be the best representation of the product. Forming the pattern selection as an optimization problem, which co-optimizes a number of objective functions reflecting modelers’ insight and expertise, has shown to produce models with equivalent quality to the traditional plan of record (POR) set but in a less time.
With ever shrinking critical dimensions, half nm OPC errors are a primary focus for process improvement in computational lithography. Among many error sources for 2x and 1x nodes, 3D mask modeling has caught the attention of engineers and scientists as a method to reduce errors at these nodes. While the benefits of 3D mask modeling are well known, there will be a runtime penalty of 30-40% that needs to be weighed against the benefit of optical model accuracy improvements. The economically beneficial node to adopt 3D mask modeling has to be determined by balancing these factors. In this paper, a benchmarking study has been conducted on a 20nm cut mask, metal and via layers with two different computational lithography approaches as compared with standard thin-mask approximation modeling. Besides basic RMS error metrics for model calibration and verification, through pitch and through size optical proximity behavior, through focus model predictability, best focus prediction and common DOF prediction are thoroughly evaluated. Runtime impact and OPC accuracy are also studied.
Process models have been in use for performing proximity corrections to designs for placement on lithography masks for
a number of years. In order for these models to be used they must provide an adequate representation of the process
while also allowing the corrections themselves to be performed in a reasonable computational time. In what is becoming
standard Optical Proximity Correction (OPC), the models used have a largely physical optical model combined with a
largely empirical resist model. Normally, wafer data is collected and fit to a model form that is found to be suitable
through experience. Certain process variables are considered carefully in the calibration process-such as exposure dose
and defocus - while other variables-such film thickness and optical parameter variations are often not considered. As
the semiconductor industry continues to march toward smaller and smaller dimensions-with smaller tolerance to errorwe
must consider the importance of those process variations. In the present work we describe the results of experiments
performed in simulations to examine the importance of many of those process variables which are often regarded as
fixed. We show examples of the relative importance of the different variables.
Depth of focus has always been of great concern in lightography as a result of processes optimized for specific feature dimensions and pitches. Insertion of sub-resolution assist features (SRAFs) or scatter bars ois a common technique used to equalize DOF through the variety of geometries used in a design. SRAFs can be inserted into the layout by a variety of means ranging from methods based on simple rule-tables to full-fledged layout simulations. Various tools are available from electronic design automation (EDA) vendors that are capable of placing srafs based on elaborate simulations of the design layout, but, a tool that can determine rule-table is not available. Each resolution enhancement technique (RET) engineer has his/her own methodology of extracting rules based on simulation of a large layout with design and sraf rule variations. Significant computational resources are required to carry-out these extensive simulations affecting the time required to formulate the rule table and restricting the variation that can be considered for the simulations. In this paper, we discuss an efficient method which overcomes this problem by searching in the design and dsraf rule domain to obtain a comprehensive set of sraf rules, thereby resulting in a better rule-set by using significantly lesser computational resources.
The process of preparing a sample plan for optical and resist model calibration has always been tedious. Not only
because it is required to accurately represent full chip designs with countless combinations of widths, spaces and
environments, but also because of the constraints imposed by metrology which may result in limiting the number of
structures to be measured. Also, there are other limits on the types of these structures, and this is mainly due to the
accuracy variation across different types of geometries. For instance, pitch measurements are normally more accurate
than corner rounding. Thus, only certain geometrical shapes are mostly considered to create a sample plan. In addition,
the time factor is becoming very crucial as we migrate from a technology node to another due to the increase in the
number of development and production nodes, and the process is getting more complicated if process window aware
models are to be developed in a reasonable time frame, thus there is a need for reliable methods to choose sample plans
which also help reduce cycle time.
In this context, an automated flow is proposed for sample plan creation. Once the illumination and film stack are defined,
all the errors in the input data are fixed and sites are centered. Then, bad sites are excluded. Afterwards, the clean data
are reduced based on geometrical resemblance. Also, an editable database of measurement-reliable and critical structures
are provided, and their percentage in the final sample plan as well as the total number of 1D/2D samples can be
predefined. It has the advantage of eliminating manual selection or filtering techniques, and it provides powerful tools
for customizing the final plan, and the time needed to generate these plans is greatly reduced.
As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process
windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC
verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust
solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively
impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and
verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process
robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable
first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by
identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not
catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable
of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while
maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented
for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC.
Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen
the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process
variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.
Performing model-based optical proximity correction (MBOPC) on layouts has become an integral part of
patterning advanced integrated circuits. Earlier technologies used sparse OPC, the run times of which explode when the
density of layouts increases. With the move to 45 nm technology node, this increase in run time has resulted in a shift to
dense simulation OPC, which is pixel-based. The dense approach becomes more efficient at 45nm technology node and
beyond. New OPC model forms can be used with the dense simulation OPC engine, providing the greater accuracy
required by smaller technology nodes. Parameters in the optical model have to be optimized to achieve the required
accuracy. Dense OPC uses a resist model with a different set of parameters than sparse OPC. The default search ranges
used in the optimization of these resist parameters do not always result in the best accuracy. However, it is possible to
improve the accuracy of the resist models by understanding the restrictions placed on the search ranges of the physical
parameters during optimization. This paper will present results showing the correlation between accuracy of the models
and some of these optical and resist parameters. The results will show that better optimization can improve the model
fitness of features in both the calibration and verification set.
The lithographic processes and resolution enhancement techniques (RET) needed to achieve pattern fidelity are
becoming more complicated as the required critical dimensions (CDs) shrink. For technology nodes with smaller
devices and tolerances, more complex models and proximity corrections are needed and these significantly increase
the computational requirements. New simulation techniques are required to address these computational challenges.
The new simulation technique we focus on in this work is dense optical proximity correction (OPC). Sparse OPC
tools typically require a laborious, manual and time consuming OPC optimization approach. In contrast, dense OPC
uses pixel-based simulation that does not need as much manual setup. Dense OPC was introduced because sparse
simulation methodology causes run times to explode as the pattern density increases, since the number of simulation
sites in a given optical radius increases.
In this work, we completed a comparison of the OPC modeling performance and run time for the dense and the
sparse solutions. The analysis found the computational run time to be highly design dependant. The result should
lead to the improvement of the quality and performance of the OPC solution and shed light on the pros and cons of
using dense versus sparse solution. This will help OPC engineers to decide which solution to apply to their
particular situation.
Optical Proximity Correction (OPC) Model Calibration has required an increasing number of measurements as the
critical dimension tolerances have gotten smaller. Measurement of two dimensional features have been increasing at a
faster rate than features with one dimensional character as the technologies require better accuracy in the OPC models
for line-end pull-back and corner rounding. New techniques are becoming available from metrology tool manufacturers
to produce GDSII contours of shapes from wafers and modeling software has been improved to use these contours.
The challenges of implementing contour generation from the SEM tools will be discussed including calibration methods,
physical dimensions, algorithm derivations, and contour registration, resolution, scan direction, and parameter space
coverage.
Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits manufactured with optical lithography technology. The accuracy of these models highly depends on the experimental data used in the model development and on the appropriate selection of the model parameters. The optical and resist model parameters selected during model build have a significant impact on the OPC model accuracy, run time, and stability. In order to avoid excessively high run times as well as ensure acceptable results, a compromise must be made between OPC run time and model accuracy. The modeling engineer has to optimize the necessary model parameters in order to find a good trade-off that achieves acceptable accuracy with reasonable run time. In this paper, we investigate the effect of some selected optical and resist model parameters on the OPC model accuracy, run time, and stability.
Optimal Proximity Correction (OPC) models are calibrated with Scanning Electron Microscope (SEM) data where the measurement uncertainty vary among pattern types (i.e., line versus space, 1D versus 2D and small versus large). The quality of the SEM measurement uncertainty's impact on OPC model integrity is mitigated through a weighting scheme. Statistical methods such as relating the weight to the SEM measurements standard deviation require more measurements per calibration structure than economically feasible. Similarly, the use of experience and engineering judgment requires many iterations before some reasonable weighting scale is determined. In this paper we present the results of OPC model fitness statistics associated with metrology based weights (MtBW) versus model based weights (MBW). The motivation for the latter approach is the promise for an unbiased, consistent, and efficient estimate of the model parameters.
Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits that are manufactured with optical lithography technology. The accuracy of these models depends highly on the experimental data used in the model development (model calibration) process. The calibration features are weighted relative to each other depending on many aspects, this weighting plays an important role in the accuracy of the developed models.
In this paper, the effect of the feature weighting on OPC models is studied. Different weighting schemes are introduced and the effect on both the optical and resist models (specifically the resist model coefficients) is presented and compared. The effect of the weighting on the overall model fitting was also investigated.
As lithography pushes to smaller and smaller features under the guidance of Moore's Law, patterned features smaller than the wavelength of light must be routinely manufactured. Lithographic yield in this domain is directly improved with the application of OPC (Optical and Process Correction) to the pattern data. Such corrections generally assume that the mask can reproduce these features exactly. The Mask Error Enhancement Factor (MEEF) serves to amplify mask errors, and can reduce the benefits of OPC in some circumstances. In this paper, we present the characterization of the MEEF for 65nm technology attenuated phase shift mask to figure out how to better set mask specs from an OPC perspective and how to measure the masks relative to these specs and try to figure out new ways to reduce model sensitivity to mask deviations for metal level.
In conventional Optical and Process Correction (OPC), models are calibrated with the CD measurement from the “good” printable patterns. Predictions of process window loss are based on extrapolation from the “good” region into the failure region. The extrapolation is always a less accurate process than interpolation. In this paper, we utilize the experimental pass/fail data to build models that accurately identify and predict printing failures. We developed a methodology and a formal apparatus for failure modeling. It is found that two or more aerial image shape parameters are required to describe all failure mechanisms for a sub-100nm process. This empirical failure model is currently applied to Optical Rule Checking (ORC) of the post-OPC layout. It also can be used to constrain layout corrections in the future.
While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.
This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.
X-ray exposures performed at IBM's Advanced Lithography Facility (ALF) in Hopewell Junction, New York has led to the ability to routinely print sub 250nm discrete devices in photoresist. When fully processed, the resulting electrical channel length for these devices is below 150nm leading to average switching delays of 35 picoseconds. Sub 150nm devices with resulting electrical channel lengths of 100nm have also been made producing switching delays of 20 picoseconds, which are among the fastest reported in CMOS technology. In addition to the discrete devices, fully functional 0.25um 64Kb SRAMs were fabricated with an approximate 40 percent chip yield on the best wafer. Recent improvements in the overall lithographic process have enabled the gate line to be printed at sub 125nm. The resulting electrical channel is below 100nm. Device performance is expected to be faster at these smaller dimensions. The results obtained are based on several lots of 200mm wafers processed with the use of mix and match (x-ray to optical) steppers. The results can be viewed as current x-ray lithography in ALF.
Electrical linewidth measurements of etched, N+-doped polysilicon submicron lines were carried out to study the effects of dose and gap on exposure latitude in proximity X-ray lithography. Isolated lines and equal line/space pairs having linewidths from 0.15 micrometers to 0.35 micrometers on the X-ray mask were printed in APEX-M resist at gaps ranging from 26 micrometers to 34 micrometers using a Karl Suss stepper. Lithography was carried out at the IBM Advanced Lithography Facility using the Helios 1 synchrotron. Low voltage scanning electron microscopy (SEM) measurements in top-down mode using the linear regression algorithm are compared to electrical linewidth measurements. Reactive-Ion Etch bias is determined by comparing top-down SEM of resist after exposure, on both 50 and 330-nm-thick polysilicon, to top-down SEM after etching. Both resist and etched line profiles are examined in cross section using SEM. The etch bias and the change in line profiles were found to account for most of the offset between the SEM and the electrical linewidth measurements. The results of SEM-measured averaged across the field, were also compared to two-dimensional aerial images (determined using average SEM-measured mask linewidths) and resist dissolution simulations to examine simulation accuracy.
A joint Motorola/IBM experiment was performed in mix-and-match lithography across widely separated locations. A simple pattern placement metrology data set was created, and x-ray masks were manufactured according to this data. The same data was converted into a 5x reticle and optically stepped on wafers. The x-ray mask was designed to print upon two optical fields with one x-ray exposure. The x-ray mask was aligned to the wafers to produce box-in- box images for overlay metrology. The main overlay problems encountered were systematic offsets between x-ray and optical images, and average magnification error of approximately 8 ppm. The magnification error is substantial because of the 3 degree(s)C temperature difference between the optical stepper stage and the x-ray mask-writer. In an actual device run, the magnification differences will be removed by compensation in the e-beam writing of the x-ray mask. Offsets will be removed by use of a send-ahead wafer to determine the correct offset alignment in the x-ray stepper.
X-ray lithography using a synchrotron light source has received considerable attention in recent years as a method for producing semiconductor device dimensions smaller than 0.35 microns. A number of synchrotrons or Electron Storage Rings (ESR) have been built around the world as possible light sources for lithographic applications. IBM has built its Advanced Lithography Facility (ALF) for the purpose of exploring synchrotron based X-ray lithography for device manufacturing. The ALF has the superconducting HELIOS compact storage ring, built by Oxford Instruments Ltd, at its center. The subject of the present paper is the design of the beamlines which connect this synchrotron light source to the Step- and- Repeat Aligner/exposure (SRA) tool where the device wafers are exposed to the synchrotron light.
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