Ms. Ivanie Mendes Profile

Ivanie Mendes

at CEA-LETI

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Author

Publications (8)

Proceedings Article | 10 April 2024 Poster

Impact of process parameters on grayscale MEEF

Ujwol Palanchoke, Florian Tomaso, Yorrick Exbrayat, Gaby Bélot, Marie-Line Pourteau, Ivanie Mendes, Juline Saugnier, Aurélien Fay, Sébastien Bérard-Bergery, Elodie Sungauer, Charlotte Beylier, Rémi Coquand, Arthur Bernadac

Proceedings Volume PC12956, PC129560Y (2024) https://doi.org/10.1117/12.3010850

KEYWORDS: 3D mask effects, Grayscale lithography, 3D modeling, Data modeling, 3D microstructuring, 3D acquisition, Semiconductors, Profilometers, Process control, Photoresist processing

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Proceedings Article | 9 April 2024 Poster + Paper

Manufacturing of 3D submicronic structures at wafer scale

Diana Fernandez Rodas, Jérôme Rêche, Ivanie Mendes, Raluca Tiron

Proceedings Volume 12956, 129560L (2024) https://doi.org/10.1117/12.3009978

KEYWORDS: Nanoimprint lithography, Manufacturing, Atomic force microscopy, Electron beam lithography, Deformation, Shrinkage, Semiconducting wafers, Scanning electron microscopy, Photoresist processing, Standards development, Grayscale lithography

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Proceedings Article | 9 April 2024 Presentation + Paper

Characterization and mitigation of local wafer deformations introduced by direct wafer-to-wafer bonding

Richard van Haren, Suwen Li, Mart Baars, Blandine Minghetti, Leon van Dijk, Ivanie Mendes, Karine Abadie, Marie-Line Pourteau, Gaëlle Mauguen, Michael May, Viorel Balan, Frank Fournel, Laurent Pain, Thomas Plach, Gernot Probst, Markus Wimplinger

Proceedings Volume 12956, 1295606 (2024) https://doi.org/10.1117/12.3010477

KEYWORDS: Wafer bonding, Semiconducting wafers, Distortion, Scanners, Silicon, Optical alignment, Deformation, Adhesion, Etching, Metrology

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A new application in the semiconductor industry that received quite some traction the past few years is bringing the transistor power delivery network to the backside of the wafer. The big gain of this change is that it frees up real estate on the frontside of the wafer, enabling a further increase of the transistor density. This so-called Back-Side Power Delivery Network (BS-PDN) application is quite challenging since it requires a direct wafer-to-wafer bonding process module. To get access to the transistor from the backside, a device wafer needs to be flipped and bonded to a carrier wafer followed by an annealing step. After these processing steps, the original substrate of the device wafer is removed by grinding and etch steps. This will enable access to the transistors from the backside of the wafer. The wafer processing continues by conventional layer deposition, lithography and etch steps, this time on the flipped wafer. Unfortunately, the bonding process module that includes the actual direct wafer-to-wafer bonding step itself, will also introduce a distortion in the device layer that has been transferred to the carrier wafer. Since the on-product overlay requirement for the first exposed layer on the backside to one of the front-side layers is tight (<10-nm today and <<5-nm in the foreseeable future), a deep understanding of the origin of the distortion fingerprint after bonding is required. In our previous work, we presented a method to isolate the distortion fingerprint due to bonding from the remaining other overlay contributors. The fingerprint we observed after linear corrections had a typical magnitude ranging from 50 to 80-nm. A clear 4-fold symmetry was observed that could be attributed to the crystal orientation of the (100) silicon substrate. We demonstrated that the scanner wafer alignment model is very capable of correcting the global 4-fold wafer distortion fingerprint. Residual levels of less than ~15-nm were shown. These residuals could be further reduced by applying a correction per exposure (CPE) recipe. We showed that performance levels of less than ~6-nm (99.7%) and ~10-nm (max) could be achieved after a 33-parameter per exposure field self-correction. The resulting wafer plots nicely revealed how to improve the overlay performance further. An increased level of residuals was found in the wafer center and at the wafer edge. In the current paper, we build upon our previous work and continue the investigation on the remaining overlay contributors that were identified previously. This time, the focus will be on the local wafer deformations that are visible after the direct wafer-to-wafer bonding step. By local we mean the distortions that manifest themselves over a very short spatial range. These local distortions cannot easily be corrected by the scanner and are typically present close to the wafer center and the wafer edge. We know that the local wafer deformation close to the wafer center is caused by the bonding pin that initiates the bond wave. To characterize the center distortion signature, we varied many experimental parameters to see the impact. We will show the impact of the die layout, the rotation of the top wafer by a 45-degrees, wafer surface properties, and substrate choice of the carrier wafer. The latter is interesting, we evaluated both (100) and (111) carrier wafers. Although the prime focus will be to improve the overlay performance on the center of the wafer, we monitor the impact of the experimental settings on the wafer edge and remaining part of the wafer as well. We present a path forward to mitigate the local distortions such that they will not be blocking for high volume production.

Proceedings Article | 1 May 2023 Presentation + Paper

Mask errors impact on grayscale lithography patterning

Ujwol Palanchoke, Gaby Bélot, Sébastien Bérard-Bergery, Juline Saugnier, Elodie Sungauer, Charlotte Beylier, Florian Tomaso, Marie-Line Pourteau, Ivanie Mendes, Rémi Coquand, Arthur Bernadac

Proceedings Volume 12497, 124970N (2023) https://doi.org/10.1117/12.2657600

KEYWORDS: Critical dimension metrology, 3D mask effects, Microlens, Design and modelling, Cadmium, Scanning electron microscopy, Semiconducting wafers, Error analysis, 3D acquisition, Grayscale lithography

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Proceedings Article | 27 April 2023 Poster + Paper

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

Viorel Balan, Florent Michel, Ivanie Mendes, Celine Lapeyre, Lionel Vignoud, Ronald Otten, Orion Mouraille, Leon van Dijk, Blandine Minghetti, Jerome Depre, Richard van Haren

Proceedings Volume 12496, 1249633 (2023) https://doi.org/10.1117/12.2658296

KEYWORDS: Annealing, Semiconducting wafers, Metrology, Distortion, Overlay metrology, Deformation, Chemical mechanical planarization, Silicon, Optical interferometry, Manufacturing

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Proceedings Article | 27 April 2023 Poster + Paper

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Richard van Haren, Suwen Li, Blandine Minghetti, Leon van Dijk, Klaas Brantjes, Frank Fournel, Gaëlle Mauguen, Ivanie Mendes, Céline Lapeyre, Marie-Line Pourteau, Michael May, Laurent Pain, Karine Abadie, Thomas Plach, Markus Wimplinger

Proceedings Volume 12496, 124962C (2023) https://doi.org/10.1117/12.2657422

KEYWORDS: Wafer bonding, Semiconducting wafers, Scanners, Silicon, Distortion, Optical alignment, Transistors, Oxides, Crystals, Etching

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Apart from the ever-continuing lateral scaling in the xy-plane to increase the transistor density, additional new concepts find their way to the semiconductor industry too. These concepts are based on making more use of the third dimension. One relatively simple idea would be to create a second layer of transistors to double the transistor density. However, the material requirements are high and the quality of the layer deposition by conventional Chemical Vapor Deposition (CVD) techniques is insufficient. Another application to free up real estate, enabling a smaller cell size and hence an increased transistor density, is to power-up the transistors from the backside. The power rails for logic devices are historically defined in the first Metal layer and consume quite some space. Bringing the power rails to the backside will free up space. However, access to the transistor layer from the backside of the wafer is far from trivial due to the presence of a 775-μm thick silicon substrate. The answer to the challenges mentioned above is wafer-to-wafer direct bonding. Although this technique is not new and already widely used in the semiconductor industry to manufacture CMOS Image Sensors (CIS), it currently finds its way to the high-end logic markets. In case of layer transfer, a crystalline silicon layer is created by bonding a Silicon-On- Insulator (SOI) wafer to the already existing device wafer. After the bonding step, the substrate of the SOI wafer will be removed leaving the crystalline silicon layer behind. Access to the transistor layer from the wafer backside can be enabled by wafer-to-wafer bonding as well. To this end, a completed device wafer will be bonded to an (un-patterned) carrier wafer. The substrate of the original device wafer will be removed, enabling access from the backside. Wafer-towafer bonding applications can only be enabled in case the induced wafer deformations are low or when they can easily be corrected during the subsequent exposures on the scanner. At CEA-Leti, a dedicated test vehicle process flow has been developed to characterize the wafer bonding-induced distortion fingerprints for both the layer transfer and the backside power delivery network applications. The wafer process flow has been simplified without losing the industry relevant on-product overlay challenges. Wafers have been created to enable an extremely dense characterization of the wafer bonding induced fingerprint. The methodology we applied enables us to isolate the wafer bonding induced distortion fingerprint, something that is difficult to do in a production environment. The Back-Side Power Delivery Network (BS-PDN) application is the most challenging one. The initial raw measured wafer distortion fingerprints are around 60 to 80-nm. These numbers can already be easily brought down by scanner corrections to ~15-nm (mean+3σ) without too much effort. However, these numbers are too large for the 2-nm technology node and beyond, and further improvement is required. The goal of this paper is to present the path forward to bring the bonding induced wafer distortion levels to 10-nm and below. We show the capability of the latest and greatest EVG bonding tool hardware and recipe settings available at the time of running the experiments in combination with the correction capability an ASML 0.33NA scanner.

Proceedings Article | 26 May 2022 Poster + Paper

Model-based contour extraction: an enabler for very low-frame SEM images metrology

Élie Sezestre, Juline Scoarnec, Jonathan Pradelles, Loïc Perraud, Aurélien Fay, Sébastien Bérard-Bergery, Jessy Bustos, Jean-Baptiste Henry, Olivier Dubreuil, Ivanie Mendes, Charles Valade, Alexandre Moly, Alice Batte, Nivea Schuch, Frederic Robert, Thiago Figueiro

Proceedings Volume 12053, 120531G (2022) https://doi.org/10.1117/12.2616527

KEYWORDS: Scanning electron microscopy, Metrology, Image processing, Calibration, Optical proximity correction, Edge detection, Mathematical modeling, Evolutionary algorithms, Detection and tracking algorithms

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Among metrology tools in the semi-conductor manufacturing, critical dimension scanning electron microscopes (CD-SEM) are the most broadly used, especially due to their high resolution, low destructivity, and high throughput. Contour metrology on CD-SEM images has become essential for characterization, modelling, and control of advanced lithography processes. In particular, OPC model’s accuracy can be highly improved using contours metrology. One of the issues when dealing with CD-SEM metrology is that the results are noise sensitive. Moreover, diminishing noise in CD-SEM acquisition leads to resist shrinkage due to exposure time increase. In addition, post-treatment of these shrinkage effects requires compensation algorithms such as artificial intelligence (AI)- driven algorithms, that are another contributor to the error budget of metrology systems. There is thus a need for an accurate, robust to noise, and purely deterministic edge detection algorithm. In this article, we evaluate the benefits of relying on a model-based contour extraction approach for performing measurements. This approach is applied onto both synthetic and experimental CD-SEM images with various patterns (mostly 2D) and noise levels to assess the influence of image integration (frame number) on the contour detection and CD measurement. We demonstrate that a model-based contour extraction algorithm is able to precisely characterize SEM-induced 2D resist shrinkage. We observe that this model-based approach is more robust to noise than standard algorithms by 21% on synthetic data and by 36% on experimental data. Another way of seeing it is, while keeping the same precision, a model-based contour extraction approach can significantly reduce the requested image frame number. The benefits of adopting this approach range from reducing the shrinkage effects to improving SEM image acquisition time. Eventually, no step of shrinkage modelling calibration nor AI-driven image post processing are needed which implies a gain on simplicity and avoids modelling errors.

Proceedings Article | 26 May 2022 Poster + Paper

Pattern customization on 193 immersion lithography by negative tone development process and multiple exposures

Ivanie Mendes, Michael May, Jérôme Rêche, Raluca Tiron, Aurélien Sarrazin, Olivier Dubreuil

Proceedings Volume 12051, 120510Q (2022) https://doi.org/10.1117/12.2614018

KEYWORDS: Reticles, Lithography, Semiconducting wafers, Scanners, Silicon, Overlay metrology, Scanning electron microscopy, Process control, Image processing, Photomasks, Immersion lithography

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