In order to adapt to the third generation of infrared focal plane readout circuit design, this paper designs a 640x512-5μm InGaAs short-wave infrared focal plane readout circuit design based on 0.18μm standard technology. Based on the analysis of each module, the design focuses on the pixel unit and the readout mode of the array. Noise reduction and gain amplification are realized by pseudo correlation double sampling technology. Finally, the design of four - channel output simulation circuit. According to the simulation results, the readout rate is 10MHz, the system default working frame frequency is 54Hz, the output swing is 1.7V, and the linearity is more than 99.9%.
Infrared imaging technology has an increasingly wide range of needs in application scenarios such as tracking and detection of high-speed targets and readout of region of interest, and system applications often have requirements for small size and low power consumption. In order to increase the frame rate of the IR detector and solve the difficulty of high power consumption faced at high speed readout, this paper proposes a programmable arbitrary windowing IP module based on a standard digital IC design and achieves ultra-low power optimization of the column-level module of the readout circuit through time-sharing multiplexing techniques. The overall design is a mixture of analogue and digital circuits, with compromises to optimize the area, noise and gain of the circuit, resulting in the integration of analogue and digital circuit layouts. In this paper, a low noise, high speed programmable arbitrary windowing ROIC has been fabricated in the 0.18μm CMOS process, the pixel array is 640×512 and the pixel pitch is 15μm. It is coupled with a short-wave infrared InGaAs detector chip to form a FPA assembly and tested. The results show that the readout rate is greater than 15MHz, the column-level power consumption is only 15mW, the total power consumption is less than 100mW, and the windowing function can be specified in any area with a minimum windowing size of 8×8.
SAR ADC has the characteristics of simple structure, low power consumption, high energy efficiency and good process compatibility. Nowadays, more and more scenarios have higher requirements for the accuracy of SAR ADC. A 14bits SAR ADC with calibration function was designed based on a 0.18μm CMOS process. Design a DAC with a segmented non-binary redundant architecture. Segmented DACs effectively reduce area overhead, while non-binary weighting reduces the effect of capacitor mismatched accuracy, thereby improving ADC accuracy. The simulation condition is that the sampling rate is 1MSPS, and the simulation results show that: Using this calibrated SAR structure, the ENOB is 13.34bits, the SNR is 74.03dB, the SFDR is 81.36dB, and the THD is -79.20dB.
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