Dr. Guillaume Schelcher Profile

Dr. Guillaume Schelcher

at imec

SPIE Involvement:

Author

Publications (9)

Proceedings Article | 12 November 2024 Presentation + Paper

Pattern selection strategy by clustering for logic EPE monitoring

Roy Anunciado, Konstantin Nechaev, Reza Sahraeian, Jeroen Schouwenberg, Guillaume Schelcher, Shubhankar Das, Wei Peng, Stefan van der Sanden, Harm Dillen

Proceedings Volume 13215, 1321508 (2024) https://doi.org/10.1117/12.3034649

KEYWORDS: Design, Logic, Optical proximity correction, Critical dimension metrology, Logic devices

Read Abstract +

Proceedings Article | 12 November 2024 Presentation + Paper

Single exposure EUV patterning optimization and defect inspection of hexagonal contact hole arrays using voltage contrast metrology

Shubhankar Das, Victor Blanco, Bappaditya Dey, Xiang Liu, Guillaume Schelcher, Danilo De Simone

Proceedings Volume 13215, 132150B (2024) https://doi.org/10.1117/12.3034189

KEYWORDS: Transmission electron microscopy, Scanning electron microscopy, Etching, Defect detection, Defect inspection, Extreme ultraviolet lithography, Metrology, Inspection, Semiconducting wafers, Optical lithography

Read Abstract +

Proceedings Article | 10 April 2024 Presentation + Paper

Feature grouping to enable edge placement error-aware process control in multi-feature logic use case

Guillaume Schelcher, Marsil Athayde, Stijn Schoofs, Jeff Hsia, Zuan Khalik, Fahong Li, Konstantin Nechaev, Reza Sahraeian, Amir-Hossein Tamaddon, Victor Blanco, Stefan van der Sanden, Yichen Zhang, Roy Anunciado, Harm Dillen, Philippe Leray

Proceedings Volume 12955, 129550O (2024) https://doi.org/10.1117/12.3010421

KEYWORDS: Semiconducting wafers, Overlay metrology, Cross validation, Process control, Logic, Metrology, Simulations, Scanning electron microscopy, Lithography

Read Abstract +

Proceedings Article | 1 December 2022 Presentation + Paper

Early defect detection for EUV self-aligned litho-etch litho-etch patterning with EPE

Roy Anunciado, Jisun Lee, Ellaheh Barzegar, Stefan van der Sanden, Guillaume Schelcher, Stijn Schoofs

Proceedings Volume 12292, 122920J (2022) https://doi.org/10.1117/12.2637772

KEYWORDS: Line edge roughness, Etching, Semiconducting wafers, Optical lithography, Critical dimension metrology, Amorphous silicon, Scanning electron microscopy, Dielectrics, Overlay metrology, Photomasks

Read Abstract +

Proceedings Article | 22 February 2021 Presentation

Electrical validation of massive E-beam defect metrology in EUV-patterned interconnects

Nicola Kissoon, Etienne De Poortere, David Hellin, Stefan Decoster, Gayle Murdoch, Stephane Lariviere, Elisabeth Camerotto, Sandip Halder, Philippe Leray, Malgorzata Jurczak, Guillaume Schelcher

Proceedings Volume 11611, 116110Q (2021) https://doi.org/10.1117/12.2584807

KEYWORDS: Metrology, Inspection, Ruthenium, Metals, Extreme ultraviolet, Etching, Electron beam lithography, Defect detection

Read Abstract +

Proceedings Article | 25 June 2019 Open Access

Machine learning for predictive electrical performance using OCD (Erratum)

Sayantan Das, Joey Hung, Sandip Halder, Guillaume Schelcher, Roy Koret, Igor Turovets, Mohamed Saib, Anne-Laure Charley, Matthew Sendelbach, Avron Ger, Philippe Leray

Proceedings Volume 10959, 1095932 (2019) https://doi.org/10.1117/12.2541616

KEYWORDS: Machine learning, Metrology, Inspection, Process control, Optical lithography, Capacitance, Lithography

Read Abstract +

DOWNLOAD PAPER

Proceedings Article | 26 March 2019 Paper

Machine learning for predictive electrical performance using OCD

Sayantan Das, Joey Hung, Sandip Halder, Guillaume Schelcher, Roy Koret, Igor Turovets, Mohamed Saib, Anne-Laure Charley, Matthew Sendelbach, Avron Ger, Philippe Leray

Proceedings Volume 10959, 109590F (2019) https://doi.org/10.1117/12.2515806

KEYWORDS: Machine learning, Semiconducting wafers, Capacitance, Resistance, Critical dimension metrology, Etching, Process control, Diffractive optical elements, Oxides, Scatterometry

Read Abstract +

Proceedings Article | 26 March 2019 Presentation

Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)

Cyrus Tabery, Vito Rutigliani, Simon Hastings, Etienne de Poortere, Luke Wang, Philippe Leray, Guillaume Schelcher, Yongjun Wang

Proceedings Volume 10959, 109591U (2019) https://doi.org/10.1117/12.2516613

KEYWORDS: Overlay metrology, Metrology, Logic, Copper, Inspection, Process modeling, Scanning electron microscopy, Wafer inspection, Error analysis, Photomasks

Read Abstract +

Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.

Proceedings Article | 20 March 2018 Presentation + Paper

Co-optimization of exposure dose and etch process for SAQP pitch walk control

Mark John Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Liesbeth Reijnen, Kaushik Kumar, Marc Demand, Carlos Fonseca, Florin Cerbu, Guillaume Schelcher, Christophe Beral

Proceedings Volume 10587, 1058704 (2018) https://doi.org/10.1117/12.2297345

KEYWORDS: Etching, Semiconducting wafers, Lithography, Diffractive optical elements, Plasma, Optical lithography, Atomic layer deposition, Critical dimension metrology, Image processing, Deposition processes

Read Abstract +

Spacer-assisted pitch multiplication is a patterning technique that is used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, a combination of lithography, deposition and etch processes, produce a repeating, non-uniform grating of space / line CDs. It has been shown that for spacer-assisted double patterning (SADP), where the lithography pitch is doubled, pitch walk can be reduced by controlling the exposure dose such that the uniformity of the final SADP spaces defined by the core resist mandrel (S1) is balanced with the final SADP space defined by the distance between adjacent SADP lines (S2). For higher pitch multiplications, starting with spacer-assisted quadruple patterning (SAQP) reducing systematic pitch walk with exposure dose becomes more complex.

Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.

Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.

Showing 5 of 9 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years