An automatic system that combines actions in both the image domain as well as in the layout-database domain for
accurate mask-defect analysis and application of design criticality will be presented. In this paper we will emphasize the
qualification and calibration of the system and its various pieces of functionality with the use of programmed defect
masks and low-voltage mask CD-SEM measurement data. Results on 1D and 2D programmed defects of various natures
are reported in dense layout as well as in real memory design layout. The results show that the system can accurately
extract mask CD-errors and defect sizes at a resolution far below that of the pixel-size of state-of-the-art mask-defect
inspection tools at nanometer resolution.
We will further demonstrate that mask-defect-inspection data can contain optical anomalies when defect or residual
feature sizes are smaller than the inspection wavelength. Mask inspection images then no longer show the real defect.
These anomalies can be analyzed with the system using advanced image actions.
Finally, we will demonstrate the capability to calculate the effects that defects have on final wafer printability even
without the need for input layout. Hence, model-based defect properties can be combined with rule-based defect
properties as well as multi-layer, design-based criticality-region properties for utter flexibility in defect disposition
capability.
DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product
designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful,
these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With
these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long
and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness.
An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM
optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM
model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and
silicon experiment results will be presented.
A new design for manufacturability (DfM) scheme with a lithography compliance check (LCC) and hot spot fixing (HSF) flow has been developed to guarantee design compliance for OPC and RET by combining lithography simulator, hot spot detector and layout modification tool. Hot spots highlighted by the LCC flow are removed by the HSF flow following modification rule consists of "Line-Sizing" (LS) and "Space-Sizing (SS)" that are resize value of line-width and space-width for the original pattern. In order to meet layout modification requirements at the pre- and post- tape out (T.O.) stages, the priorities individually set for the modification rules and the design rules, which provides flexibly to achieve the modification scheme desirable at each stage. For handling large data at a fast speed, Layout Analyzer (LA) and Layout Optimizer (LO) engines were combined with the HSF flow. LA is used to reconstruct the original hierarchy structure, clips off small parts of the layout that include hot spots from the original layout and sends those to LO in order to reduce the computational time and resource. LO optimizes the clipped off layout following the prioritized modification- and design-rules. The new DfM scheme was found to be quite effective for hot spot cleaning for 65nm node and beyond, since it was demonstrated that the HSF flow improved the lithography margin for the metal layer of 65nm node full-chip data by reducing number of hot spots to below 0.1% of original within about 12 hours, using 1CPU of commercially available workstation.
The requirement for the higher resolution is pushing up the NA of the projection lens, so the DOF becomes shallower and the focus budget becomes tight. On the other hand, the requirement for the higher through-put is still demanding. To achieve the best throughput, the alternate scanning exposure sequence is inevitable to current wafer scanners. To realize the alternative scanning exposure, it is necessary to perform precise focusing control even at the partial shot on the wafer edge region. A wafer edge stepwise focusing algorithm is developed. This algorithm utilizes multi-points focusing sensors and dynamically switches the focusing sensors during alternating scan exposure of the partial site on the wafer edge region. Thus the amount of the defocus on the wafer edge region is minimized. The actual performance of the wafer edge stepwise focusing algorithm is discussed. This algorithm can be used with or without pitching motion control of the wafer leveling stage. The influence of the pitching motion control to the focusing performance is also discussed.
Maintaining projection-aligners' stage grids-is critical for maximum overlay performance of production lithography. It seems that, particularly in the U.S., the industry has chosen the 'artifact-wafer' strategy as the standard technique to achieve this goal. This paper is intended to identify problems in overlay management using artifact wafers and to provide solutions to address the issues. One of the major sources that degrade accuracy in overlay management is the expansion/shrinkage of wafers and reticles. Both wafers and reticles expand during printing due to the heat delivered from the illumination source. The amount of the expansion tends to increase as the power of the illumination source increases per industry's demand on higher throughput. Wafers and reticles expand/shrink also due to environmental temperature change. The significance of wafer expansion/shrinkage in this mode has tended to be neglected. This is probably because, since it is measured and compensated by the 2nd print alignment, wafer scaling in the first print does not impact overlay performance evaluated at the shot center. Wafer expansion/shrinkage, however, does cause intra-shot scaling errors in overlay. And more importantly, since artifact wafers serve as absolute stage-grid-references, their expansion/shrinkage directly impact accuracy of overlay management. Reticle expansion/shrinkage due to temperature difference between where the reticles were created and where they are used along with reticle manufacturing errors causes inaccuracy in intra- shot performance evaluation. As product design rules continues to tighten, the intra-shot overlay performance can no longer be neglected. The impacts of reticle- and wafer-elasticity on total overlay management will be discussed. Multiple techniques to address the elasticity issues will be demonstrated. The discussion will conclude with recommendations for generation and usage of the artifact wafers.
A novel technique to characterize variations of the spatial (partial) coherence (sigma) across the image field in modern steppers and scanners has been developed and experimentally tested. It is based on the high sensitivity of the length L of macroscopically large diamond-shaped marks printed in photoresist to (sigma) variation. Variations in the (sigma) value across the image field lead to variations in the length of marks printed at different image field locations. The mark lengths are measured rapidly with high accuracy by a built-in optical system and then converted into (sigma) values using the calibration dependence L((sigma) ) measured in the same exposure tool. Simulation and experimental studies show that the level of projection lens aberrations in modern Nikon tools have practically no effect on (sigma) measurements obtained with this technique. Our results demonstrate that in the conventional illumination scheme, (sigma) distribution can be measured with an accuracy of 2.5%. The main advantage of the presented method is that (sigma) variation over the image field is characterized by the exposure tool itself, avoiding expensive and time-consuming SEM measurements. Moreover, since the measurement procedure is based on the wedge-shaped marks and laser scanning system currently used in Nikon tools for automated focus detection, implementation of the technique does not require any hardware or software modification.
The SIA roadmap has identified CD control as a critical issue in mask making. PBS, the most popular resist used for electron-beam mask making in the U.S., may not perform at the level required for production of 250 nm devices. There is a need in the industry today for precise CD control and tight control of CD uniformity, as well as a desire to dry etch thin films on masks. These industry trends make the use of an alternative resist attractive. A project was initiated to determine if an acceptable substitute to PBS exists. A group of eleven negative and positive resists were examined. These included chemically amplified materials, two part- novolacs, and a silicon-containing resist, among others. The resists were evaluated by using design of experiments (DOE) methodology whenever possible. All masks were exposed on 10 kV MEBES writing tools. The results were tabulated and compared, using a SEMATECH criterion for acceptability. Results are presented, including optimization of some of the materials for sensitivity, process robustness, and dry etch capability. While none of the materials met all criteria, several resists performed at a level that make them candidates to replace PBS. Several options are presented that are of interest to the mask maker contemplating process changes to accommodate 250 nm and 180 nm technologies.
LithoGraphTM, a PC-based lithography simulation software package developed by Etec Systems, is examined for its ability to be a useful tool in lithography process development. We evaluated conventional binary masks, attenuated phase shift masks (PSMs), alternate PSMs, and quadrupole illumination techniques at varying stepper parameters. As boundary conditions for the optimization, we considered image contrast, exposure-defocus latitude, exposure dose level, and optical proximity corrections. To quantify the extent of optical proximity effects, we calculated the overall exposure latitude by overlapping exposure-defocus diagrams generated at various pattern pitches.
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