Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits
are described. These results are from multi-discipline, collaborative university-industry research and emphasize
anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes
design and testing electronic monitors in silicon at 45 nm and
fast-CAD tools to identify systematic variations for entire
chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress
random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the
presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and
speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow
characterization.
Standard cell timing variations are caused by process non-idealities that are not traditionally captured within standard
timing characterization tools. This paper presents two approaches to creating variability aware standard cell timing
models in the presence of lithographic variations. The first approach uses circuit simulation of rectangular transistors to
create delay sensitivity tables to transistor length and transistor width for each cell. The second approach utilizes
lithography contours to characterize cell performance. The contour based approach is used to characterize two standard
cells in the presence of active and poly layer focus exposure variations, misalignment, and layout proximity effects. The
delay response to focus and exposure exhibits Bossung-like delay behavior and can be fit with a compact parameter
delay model. Both approaches lead to the creation of variability aware timing models in the form of delay variability
tables or compact parameter timing models. These models enable static timing analysis tools to perform critical path
variability aware delay analysis using a presumed layout-dependent distribution of process parameters with little expense in runtime.
A compact model for estimating delay variations due to double patterning lithography process variations on interconnect
layers is presented. Through process simulation and circuit analysis of one-dimensional interconnect topologies, the
delay response from focus, exposure, and overlay is studied. Using a process window defined by 10% linewidth change
from focus and exposure, and ±10% overlay error, a worst case change in delay of 3.9% is observed for an optimal
buffer circuit. It is shown that such delay responses can be modeled using a second order polynomial function of process
parameters. The impact of multiple interconnect variations in unique layout environments is studied using multiple
segments of interconnects each experiencing different variations. The overall delay responses are then examined, and it
is shown that for these layout structures, the separate variations combine in a manner that is both additive and
subtractive, thereby reducing the overall delay variations.
Exploratory prototype DfM tools, methodologies and emerging physical process models are described. The examples
include new platforms for collaboration on process/device/circuits, visualization and quantification of manufacturing
effects at the mask layout level, and advances toward fast-CAD models for lithography, CMP, etch and photomasks. The
examples have evolved from research supported over the last several years by DARPA, SRC, Industry and the Sate of
California U.C. Discovery Program. DfM tools must enable complexity management with very fast first-cut accurate
models across process, device and circuit performance with new modes of collaboration. Collaborations can be promoted
by supporting simultaneous views in naturally intuitive parameters for each contributor. An important theme is to shift
the view point of the statistical variation in timing and power upstream from gate level CD distributions to a more
deterministic set of sources of variations in characterized processes. Many of these nonidealities of manufacturing can be
expressed at the mask plane in terms of lateral impact functions to capture effects not included in design rules. Pattern
Matching and Perturbation Formulations are shown to be well suited for quantifying these sources of variation.
An exploratory Process Variation Net Scanning (PVNS) approach to estimate interconnect delay variations is presented.
It is shown that the geometrical response of lithographic nonidealities can be quickly predicted to first order with Pattern
Matching. This concept can be extended to other process nonidealities by developing Maximum Lateral Impact
Functions to capture the effects of variations in conductor sidewall angle and thickness from etch and CMP processes.
The geometrical response for each variation can then be used to model the effective change in resistance and capacitance
and perturb the corresponding values in the extracted netlist. The impact of PVNS is demonstrated using a 90nm digital
design, and the runtime analysis indicates that this approach may potentially be twice as fast as traditional extraction.
This allows for fast electrical analysis of independent process variations on different interconnect layers instead of
traditional best and worst case corner analyses.
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