Over the past few years, deep neural networks have achieved state-of-the-art accuracy in a broad spectrum of applications. However, implementing deep networks in general purpose architectures is a challenging task as they require high computational resources and massive memory bandwidth. Recently, several digital neuromorphic chips have been proposed to address these issues. In this paper, we explore sixteen prominent rate based digital neuromorphic chip architectures, optimized primarily for inference. Specific focus is on: What is the motivation to design digital neuromorphic chips? Which optimizations play a key role in improving their performance? What are the main research trends in current generation chips?
In recent years deep neural networks have shown great advances in image processing tasks. For modern datasets, these networks require long training times due to backpropagation, high amount of computational resources for weight updates, and memory intensive weight storage. Exploiting randomness during the training of deep neural networks can mitigate these concerns by reducing the computational costs without sacrificing network performance. However, a fully randomized network has limitations for real-time target classification as it leads to poor performance. Therefore we are motivated in using semi-random deep neural networks to exploit random fixed weights. In this paper, we demonstrate that semi-random deep neural networks can achieve near real-time training with comparable accuracies to conventional deep neural networks models. We find that these networks are enhanced by the usage of skip connections and train rapidly at the cost of dense memory usage. With greater memory resources available, these networks can train on larger datasets at a fraction of the training time costs. These semi-random deep neural network architectures open up an avenue for further research in utilizing random fixed weights in neural networks.
Unitary operations using linear optics have many applications within the quantum and neuromorphic space. In silicon photonics, using networks of simple beam splitters and phase shifters have proven sufficient to realize large-scale arbitrary unitaries. While this technique has shown success with high fidelity, the grid physically scales with an upper bound of O(n2). Consequently, we propose to considerably reduce the footprint by using multimode interference (MMI) devices. In this paper, we investigate the active control of these MMIs and their suitability for approximating traditionally used unitary circuits.
Multilayer Perceptron Networks with random hidden layers are very efficient at automatic feature extraction and offer significant performance improvements in the training process. They essentially employ large collection of fixed, random features, and are expedient for form-factor constrained embedded platforms. In this work, a reconfigurable and scalable architecture is proposed for the MLPs with random hidden layers with a customized building block based on CORDIC algorithm. The proposed architecture also exploits fixed point operations for area efficiency. The design is validated for classification on two different datasets. An accuracy of ~ 90% for MNIST dataset and 75% for gender classification on LFW dataset was observed. The hardware has 299 speed-up over the corresponding software realization.
The advent of nanoscale metal-insulator-metal (MIM) structures with memristive properties has given birth to a new generation
of hardware neural networks based on CMOS/memristor integration (CMHNNs). The advantage of the CMHNN
paradigm compared to a pure CMOS approach lies in the multi-faceted functionality of memristive devices: They can
efficiently store neural network configurations (weights and activation function parameters) via non-volatile, quasi-analog
resistance states. They also provide high-density interconnects between neurons when integrated into 2-D and 3-D crossbar
architectures. In this work, we explore the combination of CMHNN classifiers with manifold learning to reduce the
dimensionality of CMHNN inputs. This allows the size of the CMHNN to be reduced significantly (by ≈ 97%). We tested
the proposed system using the Caltech101 database and were able to achieve classification accuracies within ≈ 1:5% of
those produced by a traditional support vector machine.
Side-channel attacks (SCAs), specifically differential power attacks (DPA), target hardware vulnerabilities of cryptosystems. Next generation computing systems, integrated with emerging technologies such as RRAM, offer unique opportunities to mitigate DPAs with their inherent device characteristics. We propose two different approaches to mitigate DPA attacks using memristive hardware. The first approach, obfuscates the power profile using dual RRAM modules. The power profile stays almost uniform for any given data access. This is achieved by realizing a memory and its complementary module in RRAM hardware. Balancing logic, which ensures the parallel access, is implemented in CMOS. The power consumed with the dual-RRAM balancing is an order lower than the corresponding pure CMOS implementation. The second exploratory approach, uses a novel neuromemristive architecture to compute an AES transformation and mitigate DPAs. Both the proposed approaches were tested on a 128-bit AES algorithm. A customized simulation framework, integrating CAD tools, is developed to mount the DPA attacks. In both the designs, the attack mounted on the baseline architectures (CMOS only) was successful and full key was recovered. However, DPA attacks mounted on the dual RRAM modules and neuromemristive hardware modules of an AES cryptoprocessor yielded no successful keys, demonstrating their resiliency to DPA attacks.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.