Mr. Changliang Yu Profile

Changliang Yu

at Tianjin Univ

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Proceedings Article | 8 January 2008 Paper

Design and fabrication of a low crosstalk multi-channel CMOS OEIC receiver module

Haobo Zhu, Luhong Mao, Changliang Yu, Hongda Chen

Proceedings Volume 6838, 68380B (2008) https://doi.org/10.1117/12.756066

KEYWORDS: Receivers, Photonic integrated circuits, Photodetectors, Field effect transistors, Capacitance, Silicon, Sensors, Integrated circuit design, Optoelectronics, Optical interconnects

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In this paper, the design and fabrication for a high speed, low crosstalk 12 channels monolithic integrated CMOS optoelectronic integrated circuit (OEIC) receiver module is reported. The module consists of a Si-based photodetector array and front-end circuit integrated receiving chip; printed circuit board (PCB); fiber array; package and shield components. The structure of Si-based double photodiode (DPD) can speed up the receiver but at the same time make the deterioration of responsivity. The adoption of active inductors in TIA circuit can extend the -3dB bandwidth to a higher level. In particular, the design method of low crosstalk is discussed in detail. Instead of conventional isolation methods used to reduce inter-channel crosstalk, we find a novel way to cancel it by study crosstalk issues from a circuit design perspective. The chip fabricated by CSMC (a foundry in WuXi, China) 0.6μm standard CMOS process without any modification to the process or additional post-process steps. This extremely reduced chip fabrication costs. The module has the merit of high speed, low crosstalk and low cost spontaneously. The measured results show that every single channel of the receiver is able to work at bit rates about 1Gb/s. In total the monolithic integrated 12-channel OEIC receiver module can be operated at 12 Gb/s. The module can be used in ultra high speed optical interconnection system.

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