Mr. Bo-Jou Lu Profile

Bo-Jou Lu

at United Microelectronics Corp

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Author

Publications (8)

Proceedings Article | 19 March 2012 Paper

Development of Si-HM for NTD process

Wen Liang Huang, Yu Chin Huang, Bo Jou Lu, Yi Jing Wang, Yeh Sheng Lin, Chun Chi Yu, Satoshi Takeda, Yasunobu Someya, Makoto Nakajima, Yuta Kanno, Hiroyuki Wakayama, Rikimaru Sakamoto

Proceedings Volume 8325, 832523 (2012) https://doi.org/10.1117/12.916363

KEYWORDS: Lithography, Photoresist processing, Optical lithography, Semiconducting wafers, Diffusion, Manufacturing, System on a chip, Etching, Photomasks, Materials processing

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Proceedings Article | 2 April 2010 Paper

From pin-point design based critical dimension metrology toward comprehensive evaluation of IC patterning integrity

Chris Sallee, Wayne Clark, Bo Jou Lu, Vladimir Ukraintsev, Vitali Khvatkov

Proceedings Volume 7638, 76382N (2010) https://doi.org/10.1117/12.848619

KEYWORDS: Image processing, Semiconducting wafers, Scanning electron microscopy, Imaging arrays, Feature extraction, Manufacturing, Optical lithography, Critical dimension metrology, Design for manufacturability, Printing

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Proceedings Article | 4 March 2010 Paper

Immersion BARC for hyper NA applications II

Yu-Chin Huang, Kai-Lin Chuang, Tsung-Ju Yeh, Steven Wu, Bill Lin, Wen-Liang Huang, Bo-Jou Lu, E. Liu, Chun Chi Yu, Chaoyang Lin, Jeong Yun Yu, Greg Prokopowicz, Sue Ryeon Kim, Sabrina Wong, George Barclay

Proceedings Volume 7640, 76403F (2010) https://doi.org/10.1117/12.848454

KEYWORDS: Reflectivity, Metals, Line width roughness, Logic devices, Multilayers, Etching, Lithography, Control systems, Immersion lithography, Back end of line

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Proceedings Article | 15 April 2008 Paper

Line width roughness (LWR) performance of novel surface conditioner solutions for immersion lithography

Bo Jou Lu, E. T. Liu, Anson Zeng, Aroma Tseng, Steven Wu, Bill Lin, Chun Chi Yu, Ling-Jen Meng, Manuel Jaramillo, Ming-Ching Liao

Proceedings Volume 6923, 69233G (2008) https://doi.org/10.1117/12.772494

KEYWORDS: Line width roughness, Semiconducting wafers, Lithography, Immersion lithography, Standards development, 193nm lithography, Critical dimension metrology, Line edge roughness, Image processing, Lutetium

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Proceedings Article | 31 March 2008 Paper

Non-topcoat resist design for immersion process at 32-nm node

Steven Wu, Aroma Tseng, Bill Lin, Chun Chi Yu, Bo-Jou Lu, Wen-Shiang Liao, Deyan Wang, Vaishali Vohra, Cheng Bai Xu, Stefan Caporale, George Barclay

Proceedings Volume 6923, 692307 (2008) https://doi.org/10.1117/12.775542

KEYWORDS: Electron beam lithography, Photoresist processing, Polymers, Semiconducting wafers, Lithography, Immersion lithography, Water, Surface properties, Surface roughness, Thin film coatings

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Proceedings Article | 15 May 2007 Paper

Implementation of double dipole lithography for 45-nm node poly and diffusion layer manufacturing with 0.93NA

Meng-Hsiu Wu, Michael Hsu, Stephen Hsu, Bo-Jou Lu, Yung-Feng Cheng, Yueh-Lin Chou, Chuen-Huei Yang

Proceedings Volume 6607, 660731 (2007) https://doi.org/10.1117/12.729020

KEYWORDS: Photomasks, Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Resolution enhancement technologies, Lithography, Manufacturing, Calibration, Data modeling, Printing

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The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography. Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole illumination can help us to reach smaller k1 value (~0.31) and meet the process requirements of poly and diffusion layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the more challenging question should be: how to calibrate a good model from two exposure and decompose original design to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip processing, we need a robust application strategy to ensure a very tight CD control. We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node - X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a process design flow starting from the design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask data preparation. All of the work has been implemented using MaskWeaver^TM geometry engine. Additionally, we investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL process is ready for 45nm node and is well within reach to be used on next generation production environment.

Proceedings Article | 6 April 2007 Paper

Depth-of-focus (DOF) and line-width roughness (LWR) performance of novel surface conditioner solutions for immersion lithography

Bo Jou Lu, Yongfa Huang, H. Tseng, Chun Chi Yu, Ling-Jen Meng, Ming-Chi Liao, Michale Legenza

Proceedings Volume 6519, 651942 (2007) https://doi.org/10.1117/12.711938

KEYWORDS: Line width roughness, Etching, Photoresist processing, Optical proximity correction, Image processing, Semiconducting wafers, Immersion lithography, Lithography, Line edge roughness, Scanning electron microscopy

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Proceedings Article | 27 March 2007 Paper

Feasibility Study of 45nm Metal Patterning with 0.93 NA

Yung Feng Cheng, Yueh Lin Chou, Ya Ching Hou, Bo Jou Lu, Chuen Huei Yang

Proceedings Volume 6520, 65204J (2007) https://doi.org/10.1117/12.711367

KEYWORDS: Polarization, Metals, Resolution enhancement technologies, Printing, Semiconducting wafers, Logic, Image processing, Optical lithography, Line width roughness, Image resolution

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Showing 5 of 8 publications

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