A 65nm node RF and Analog CMOS process is described with advanced features for use in next generation ROICs. This process is in a unique position to enable both digital pixel ROICs and conventional ROIC architectures. The production process exists in a high-volume commercial fabrication facility and is being offered to aerospace and defense customers. Features to enable large array formats, such as stitching, up to nine layers of metal, low voltage operation are included, as well as multiple analog FETs, in particular low leakage, spanning low voltage up to 5V. Several analog features such resistors and MIM capacitors, and reconfigurable elements such as memory, e-fuse, will also be described. The platform process and device features, and special PDK features such as cryogenic models, will be related to select circuit block functions and requirements for large format applications such as cooled and uncooled ROICs.
Three-dimensional read-out integrated circuit (3D-ROIC) based advanced focal-plane-array (FPA) architectures are driven by the requirements of pixel level analog-to-digital conversion, on-chip digital-signal-processing, high framerates, low read noise, and extended dynamic range. These 3D-ROIC FPAs require hybridization of analog technology ROIC silicon wafers with digital technology ROIC silicon wafers and detectors. Small pitch vias are needed both at the topmost and bottommost surfaces of the analog wafers to facilitate these 3D-ROIC architectures. Although it is easy to build top surface vias, integration of bottom surface vias into the CMOS process flows is uncommon. In this paper, we describe the integration of tungsten-filled isolated deep-silicon-vias (iDSV) extending from metal1 to the handle wafer of the substrate in thick-film SOI based 130nm and 180nm mixed-signal CMOS processes. Major advantages of the iDSV based integration scheme reported here include ease of porting of mixed-signal designs from bulk CMOS to SOI, high density 3D-ROIC interconnect formation with via-middle integration, and an inbuilt buried-oxide etch stop layer for post wafer process thinning for iDSV reveal. These iDSVs have resistances of 2.5Ω/via, breakdown voltages exceeding 50V, and leakage currents to adjacent wells of less than 10fA/via. We report electrical results and process flow of the more complex face-to-back hybrid wafer bonding utilizing the top vias in the daughter wafer and iDSV in the mother wafer with copper direct-bond-interconnect (DBI) hybridization at 4μm pitch. We outline various 3D-ROIC integration architectures for large-format and small pixel FPAs using iDSV and DBI bonding, along with their advantages and disadvantages.
Buried channel (BC) MOSFETs are known to have better noise performance than surface channel (SC) MOSFETs when
used as source followers in modern Charge Coupled Devices (CCD). CMOS image sensors find increasing range of
applications and compete with CCDs in high performance imaging, however BC transistors are rarely used in CMOS. As
a part of the development of charge storage using BC CCDs in CMOS, we designed and manufactured deep depletion
BC n-type MOSFETs in 0.18 μm CMOS image sensor process. The transistors are designed in a way similar to the
source followers in a typical BC CCD. In this paper we report the results from their characterization and compare with
enhancement mode and “zero-threshold” SC devices. In addition to the detailed current-voltage and noise measurements,
semiconductor device simulation results are presented to illustrate and understand the different conditions affecting the
channel conduction and the noise performance of the BC transistors at low operating voltages. We show that the biasing
of the BC transistors has to be carefully adjusted for optimal operation, and that their noise performance at the right
operating conditions can be superior to SC devices, despite their lower gain as in-pixel source followers.
In this paper, we report on the highest speed 240GHz/340GHz FT/FMAX NPN which is now available for product
designs in the SBC18H4 process variant of TowerJazz’s mature 0.18μm SBC18 silicon germanium (SiGe) BiCMOS
technology platform. NFMIN of ~2dB at 50GHz has been obtained with these NPNs. We also describe the integration
of earlier generation NPNs with FT/FMAX of 240GHz/280GHz into SBC13H3, a 0.13μm SiGe BiCMOS technology
platform. Next, we detail the integration of the deep silicon via (DSV), through silicon via (TSV), high-resistivity
substrate, sub-field stitching and hybrid-stitching capability into the 0.18μm SBC18 technology platform to enable
higher performance and highly integrated product designs. The integration of SBC18H3 into a thick-film SOI
substrate, with essentially unchanged FT and FMAX, is also described. We also report on recent circuit demonstrations
using the SBC18H3 platform: (1) a 4-element phased-array 70-100GHz broadband transmit and receive chip with flat
saturated power greater than 5dBm and conversion gain of 33dB; (2) a fully integrated W-band 9-element phase-controllable
array with responsivity of 800MV/W and receiver NETD is 0.45K with 20ms integration time; (3) a 16-element 4x4 phased-array transmitter with scanning in both the E- and H-planes with maximum EIRP of 23-25 dBm at
100-110GHz; (4) a power efficient 200GHz VCO with -7.25dBm output power and tuning range of 3.5%; and (5) a
320GHz 16-element imaging receiver array with responsivity of 18KV/W at 315GHz, a 3dB bandwidth of 25GHz and
a low NEP of 34pW/Hz1/2. Wafer-scale large-die implementation of the phased-arrays and mmWave imagers using
stitching in TowerJazz SBC18 process are also discussed.
New foundry processes continue to produce smaller features and new designs. These new devices must be screened to
validate their usefulness for long lifetime use. The Failure-in-Time analysis in conjunction with foundry qualification
information can be used to evaluate foundry device lifetimes. This analysis is a helpful tool when zero failure life tests
are performed. The reliability of the device is estimated by applying the failure rate to the use conditions. JEDEC
publications.2,3,4 are the industry accepted methods.
Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array
sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in
the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out
integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which
may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors
(FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel
pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X
reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also
described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor
having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process
results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile
memory options in the CA18 technology platform are outlined.
TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more
than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production
ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology
platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and
a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low
insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM
capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for
inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors.
Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband
imaging are presented.
KEYWORDS: Readout integrated circuits, Signal processing, CMOS technology, Oxides, Resistors, Metals, Capacitors, Field effect transistors, Fourier transforms, Digital signal processing
Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low
power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high
performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide
1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization,
have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum
metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor
applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available
features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX
frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which
could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and
power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF
enabled ROICs, are also described in this paper.
TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the
mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are
described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm
and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon
resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal
integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that
maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma
models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are
described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile
broadband, phased array radar, collision avoidance radar and W-band imaging are listed.
Today's modular, mixed-signal CMOS process platforms are excellent choices for manufacturing of highly integrated,
large-format read out integrated circuits (ROICs). Platform features, that can be used for both cooled and un-cooled
ROIC applications, can include (1) quality passives such as 4fFμm2 stacked MIM capacitors for linearity and higher
density capacitance per pixel, 1kOhm high-value poly-silicon resistors, 2.8μm thick metals for efficient power
distribution and reduced I-R drop; (2) analog active devices such as low noise single gate 3.3V, and 1.8V/3.3V or
1.8V/5V dual gate configurations, 40V LDMOS FETs, and NPN and PNP devices, deep n-well for substrate isolation for
analog blocks and digital logic; (3) tools to assist the circuit designer such as models for cryogenic temperatures, CAD
assistance for metal density uniformity determination, statistical, X-sigma and PCM-based models for corner validation
and to simulate design sensitivity, and (4) sub-field stitching for large die. The TowerJazz platform of technology for
0.50μm, 0.25μm and 0.18μm CMOS nodes, with features as described above, is described in detail in this paper.
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