Currently the most widely graphene production technique is growth via Chemical Vapor Deposition (CVD) on copper thin films previously deposited by evaporation on sapphire substrates, which can yield high-quality monolayer graphene coatings. However, the transfer of graphene from the growth substrate via conventional methods making use of support/protective layers (e.g., organic polymers), lithographic masking layers and chemical etching, is a multi-step complex procedure. Here, we report the use of laser-based transfer technique, namely, Laser-Induced Forward Transfer (LIFT) for the reliable, reproducible and high-quality transfer of graphene pixels at designated areas on SiO2/Si substrates, directly from the growth substrate. LIFT is an environmentally friendly, mask-less technique and offers high resolution with high throughput. The quality of the transferred films has been inspected via SEM, Raman spectroscopy, and AFM characterization. Electrical characterization for mobility measurement will also be performed. The aim of this study is the process optimization of LIFT process parameters, such as the laser fluence. The reported results highlight the advantages of the laser-based monolayer graphene deposition methods for the on-chip integration of graphene-based photodetectors.
Graphene-based devices have garnered significant attention for their potential in numerous applications, notably in integrated photonics. For graphene devices to be used in real-world systems, it is necessary to demonstrate competitive device performance, repeatability of results, reliability, and a path to large-scale manufacturing with high yield at low cost. In this study, single-layer graphene electro-absorption modulators serve as a pivotal test vehicle to facilitate wafer-scale integration in a 300mm pilot CMOS foundry, harnessing imec silicon photonics platforms along with the 6- inch graphene transfer capabilities of Graphenea. The patterning of graphene is achieved utilizing a hardmask, with tungsten-based contacts being developed via the damascene method to facilitate CMOS-compatible manufacturing. Through an extensive analysis of inline metrology data during process development along with analysis of hundreds of devices on each wafer, the impact of specific processing steps on the performance could be identified and optimized. Subsequent to optimization, a modulation depth of 50 ± 4 dB/mm is exemplified across 400 devices, measured utilizing 5 V peak-to-peak voltage, achieving electro-optical bandwidths up to 15.1 ± 1.8 GHz for 25μm-long devices. The results achieved are comparable to lab-based record-setting graphene devices of similar design and chemical vapor deposition graphene quality. By demonstrating the reproducibility of the results across hundreds of devices, this work resolves the bottleneck of graphene wafer-scale integration. Furthermore, CMOS-compatible processing enables co-integration of graphene-based devices with other photonics and electronics building blocks on the same chip, and for high-volume low-cost manufacturing.
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