Extreme ultraviolet (EUV) lithography has been used for mass production for several years. Now the resolution limit of current 0.33 NA single exposure has been approaching. To enhance the resolution limit, high NA exposure tool has been developing. At the limit, not only the stochastic failures1, but also patterning trade-off has been becoming challenging. In this paper, to overcome the patterning trade-off of LS and CH, several approaches were demonstrated for both CAR and MOR. As for chemically amplified resist (CAR), to overcome the patterning trade-off of line and space, two different approaches were demonstrated. One was a developer rinse process optimization, and the other was a top deposition treatment during etching process. By using the two approaches, pitch 24 nm LS patterns were successfully transferred. As to CAR CH patterning, a new shrink technique during etch process was successfully tested for sub 15 nm hole patterning. No missing hole detected at 12 nm hole size by voltage contrast metrology. For tighter nodes, spin-on metal oxide resist (MOR) have been considering to be used because it offers a series of advantages. It has high sensitivity and resolution because of its high photon absorption and simple reaction mechanism. It also inherently has a higher etch resistance which enables resist thickness thinner and collapse margin higher. Spin-on process of MOR is expect to contribute high productivity which is essential for high volume manufacturing (HVM). Because defect reduction is one of the key points to enable MOR process for HVM, continuous investigation of defect mitigation has been done. For pitch 32 nm LS, the mitigation was confirmed by fine optimization with the combination of the etch process and the implementation of new under layers. As to pitch 28nm line and space, optimized illumination gave better defect process windows. Moreover, a new wet developer process was successfully proposed to prevent pitch 36 nm hexagonal pillars collapse during wet development with 25% higher EUV sensitivity.
Directed Self-Assembly (DSA) is being extensively evaluated for application in semiconductor process integration.1-7 Since 2011, the number of publications on DSA at SPIE has exploded from roughly 26 to well over 80, indicating the groundswell of interest in the technology. Driving this interest are a number of attractive aspects of DSA including the ability to form both line/space and hole patterns at dimensions below 15 nm, the ability to achieve pitch multiplication to extend optical lithography, and the relatively low cost of the processes when compared with EUV or multiple patterning options.
Tokyo Electron Limited has focused its efforts in scaling many laboratory demonstrations to 300 mm wafers. Additionally, we have recognized that the use of DSA requires specific design considerations to create robust layouts. To this end, we have discussed the development of a DSA ecosystem that will make DSA a viable technology for our industry, and we have partnered with numerous companies to aid in the development of the ecosystem. This presentation will focus on our continuing role in developing the equipment required for DSA implementation specifically discussing defectivity reduction on flows for making line-space and hole patterns, etch transfer of DSA patterns into substrates of interest, and integration of DSA processes into larger patterning schemes.
An electrical test vehicle for fabricating direct self-assembly (DSA) sub-30 nm via interconnects has been fabricated employing a soft mask grapho-epitaxy contact-hole shrink. The generation of the resist pre-pattern was carried out using 193i lithography on three different stacks and the BCP assembly was evaluated with and without template affinity control on the resist pre-pattern. After DSA shrink, the holes were transferred in a 100 nm oxide for standard Tungsten metallization for electrical characterization.
Directed Self-Assembly (DSA) is one of the most promising technologies for scaling feature sizes to 16 nm and below.
Both line/space and hole patterns can be created with various block copolymer morphologies, and these materials allow
for molecular-level control of the feature shapes—exactly the characteristics that are required for creating high fidelity
lithographic patterns. Over the past five years, the industry has been addressing the technical challenges of maturing this
technology by addressing concerns such as pattern defectivity, materials specifications, design layout, and tool
requirements. Though the learning curve has been steep, DSA has made significant progress toward implementation
in high-volume manufacturing.
Tokyo Electron has been focused on the best methods of achieving high-fidelity patterns using DSA processing. Unlike
other technologies where optics and photons drive the formation of patterns, DSA relies on surface interactions and
polymer thermodynamics to determine the final pattern shapes. These phenomena, in turn, are controlled by the
processing that occurs on clean-tracks, etchers, and cleaning systems, and so a host of new technology has been
developed to facilitate DSA. In this paper we will discuss the processes and hardware that are emerging as critical
enablers for DSA implementation, and we will also demonstrate the kinds of high fidelity patterns typical of mainstream
DSA integrations.
Directed Self-Assembly (DSA) has become a promising alternative for generating fine lithographic patterns. Since contact holes are among the most difficult structures to resolve through traditional lithographic means, directed selfassembly applications that generate smaller contact holes are of particular interest to the industry. In this paper, DSA integrations that shrink pre-patterned contact holes were explored. The use of both block copolymers (BCPs)1 and blended polymer systems2 was considered. In addition, both wet3 and dry4 techniques were used to develop the central core out of the respective phase-separated morphologies. Finally, the hole patterns created through the various contact hole applications were transferred to substrates of interest with the goal of incorporating them into an IMEC 28 nm node via chain electrical test vehicle for direct, side-by-side comparison.
Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards LWR and pattern collapse improvement [1-10]. TEL has developed a DSA development ecosystem (collaboration with customers, consortia, inspection vendors and material suppliers) to successfully demonstrate directed PS-PMMA DSA patterns using chemo-epitaxy (lift-off and etch guide) and grapho-epitaxy integrations on 300 mm wafers. New processes are being developed to simplify process integration, to reduce defects and to address design integration challenges with the long term goal of robust manufacturability. For hole DSA applications, a wet development process has been developed that enables traditional post-develop metrology through the high selectivity removal of PMMA cylindrical cores. For line/ space DSA applications, new track, cleans and etch processes have been developed to improve manufacturability. In collaboration with universities and consortia, fundamental process studies and simulations are used to drive process improvement and defect investigation. To extend DSA resolution beyond a PS-PMMA system, high chi materials and processes are also explored. In this paper, TEL’s latest process solutions for both hole and line/space DSA process integrations are presented.
One critical problem with EUV patterning is the local CD variation of contact holes. The issue is especially problematic for patterning of sub-30nm hole dimensions. Although the EUV wavelength enables resolution of fine contact patterns, shot noise effects (both chemical and optical) result in high levels of CD non-uniformity. Directed self-assembly (DSA) offers the possibility of rectifying this non-uniformity. Since the resulting CD in this patterning approach is typically dictated by the polymer size, application of this technology in conjunction with an EUV-defined pre-pattern can theoretically improve the local CD uniformity. Integration approaches using both chemo- and grapho-epitaxy integration may be used to achieve DSA enabled uniformity improvement. The drawbacks and benefits of both approaches will be discussed. Finally, these types of DSA flows also enable frequency multiplication to achieve dense arrays from an initially sparse pattern. In this study, we will report on a variety of schemes to attain rectification and frequency multiplication.
As directed self-assembly (DSA) has gained momentum over the past few years, questions about its application to high
volume manufacturing have arisen. One of the major concerns is about the fundamental limits of defectivity that can be attained with the technology. If DSA applications demonstrate defectivity that rivals of traditional lithographic
technologies, the pathway to the cost benefits of the technology creates a very compelling case for its large scale
implementation. To address this critical question, our team at IMEC has established a process monitor flow to track the
defectivity behaviors of an exemplary chemo-epitaxy application for printing line/space patterns. Through establishing
this baseline, we have been able to understand both traditional lithographic defect sources in new materials as well as
new classes of assembly defects associated with DSA technology. Moreover, we have explored new materials and
processing to lower the level of the defectivity baseline. The robustness of the material sets and process is investigated
as well. In this paper, we will report the understandings learned from the IMEC DSA process monitor flow.
Directed Self Assembly (DSA) using block copolymers (BCP) has received considerable attention over the past few
years as a potential complementary lithographic technique. While many are focused on adapting DSA integrations to
high volume manufacturing, the key to the technology’s success lies in its ability to generate low defect patterns. The
best way to drive the technology toward a zero defect solution is to understand the fundamentals of the block copolymer
assembly, the interactions of the block copolymer with the underlying chemical pattern, and the evaluation of process
parameters to obtain a high degree of order of the BCP morphologies. To this end, recent research has investigated
numerous material, structural, and process sensitivities of an exemplary chemo-epitaxy line/space integration. Using the
DSA flow implemented at imec, substrate properties, such as the geometry and chemistry, were studied and provided the
first results regarding the dimensions of the nano-patterns and the energetic conditions necessary to obtain good
alignment of the BCP. Additional parameters that have been explored include BCP film thickness and the bake
conditions used to execute various steps of the flow. With this work, the key parameters that drive the assembly process
have been identified. This will allow the definition of an optimized process window and materials for defect
minimization.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.