Nesting ring architecture of multichip optical network on chip for many-core processor systems

Wenzhe Li; Bingli Guo; Xin Li; Shan Yin; Yu Zhou; Shanguo Huang

doi:10.1117/1.OE.56.3.035106

31 March 2017 Nesting ring architecture of multichip optical network on chip for many-core processor systems

Wenzhe Li, Bingli Guo, Xin Li, Shan Yin, Yu Zhou, Shanguo Huang

Author Affiliations +

Funded by: National Natural Science Foundation of China (NSFC), NSFC, Natural Science Foundation of China, NSFC Program, Program for New Century Excellent Talents in University (New Century Excellent Talents Program), Beijing Nova Program, China Post-Doctoral Science Foundation, China Post Doctoral Science Foundation

Optical Engineering, Vol. 56, Issue 3, 035106 (March 2017). https://doi.org/10.1117/1.OE.56.3.035106

Abstract

Optical network on chip (ONoC) is an attractive solution for multicore/many-core processor systems due to its high power efficiency and enormous bandwidth. However, as increasing numbers of cores need to be interconnected, the scalability of a many-core processor on a single chip is limited by its process yield and power density. A multichip architecture is, therefore, proposed to improve the scalability of ONoC. In multichip architectures, the throughput and traffic delay rely on both the intrachip and interchip networks. To exploit the advantages of multichip systems, first we propose a multichip ONoC architecture for a many-core processor system that employs a nesting ring topology. The design principles of multichip systems of different sizes are then investigated to achieve higher throughput and lower delay. These principles include the number of chips and the number of cores per chip, which are considered jointly for the first time. Finally, we evaluate the performance of the proposed architecture, implemented in 240-core and 400-core systems, respectively, and compare it to two other traditional ONoC architectures with respect to throughput and end-to-end (ETE) delay. The results show that the proposed multichip system exhibits good scalability, achieves high throughput, and provides low ETE delay.

Citation Download Citation

Wenzhe Li, Bingli Guo, Xin Li, Shan Yin, Yu Zhou, and Shanguo Huang "Nesting ring architecture of multichip optical network on chip for many-core processor systems," Optical Engineering 56(3), 035106 (31 March 2017). https://doi.org/10.1117/1.OE.56.3.035106

Received: 17 August 2016; Accepted: 16 March 2017; Published: 31 March 2017

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

;

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE