Special Section Guest Editorial: Metrology and Inspection for 3-D Integrated Circuits and Interconnects

Alexander Starikov; Yi-Sha Ku

doi:10.1117/1.JMM.13.1.011201

25 March 2014 Special Section Guest Editorial: Metrology and Inspection for 3-D Integrated Circuits and Interconnects

Alexander Starikov, Yi-Sha Ku

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 13, Issue 1, 011201 (March 2014). https://doi.org/10.1117/1.JMM.13.1.011201

Abstract

Three-dimensional integration of stacked device cells in front end (FE) and of advanced metallization in back end (BE) enabled by through-silicon via (TSV) opens new paths to increased product functionality even without device shrink. But “going 3-D” also creates many new challenges for the semiconductor industry. Development of the new designs, manufacturing methods, and processes demands rapid technology and materials characterization, as well as in-line metrology and inspection for process development and control in completely new and changing applications environments.

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Alexander Starikov and Yi-Sha Ku "Special Section Guest Editorial: Metrology and Inspection for 3-D Integrated Circuits and Interconnects," Journal of Micro/Nanolithography, MEMS, and MOEMS 13(1), 011201 (25 March 2014). https://doi.org/10.1117/1.JMM.13.1.011201

Published: 25 March 2014

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