Presentation
4 October 2024 Photonic-electronic ICs for machine intelligence: devices, architectures, chip packaging
Author Affiliations +
Abstract
This presentation covers the opportunities and challenges of photonic-electronic chip-based machine intelligence acceleration hardware. We will start with a review of device-level component performance specifications such as footprint, energy consumption, reconfiguration speed, for instance. Emerging materials, when integrated monolithically into photonic waveguide circuits, show promise for next generation opto-electronic components offering high FOMs, however have high barrier to entry in for foundry PDKs. Beyond devices, we will explore a variety of architectural choices, known as co-design optimization. Parallelization strategies, smart routing, optical hardware function implementation (e.g. Fourier transformation on-chip) will be covered. Next, we explore chip packaging options including ADK and digital-twin hardware in the loop optimizations thereof. Finally, examples of prototyping will be shared and application options discussed.
Conference Presentation
© (2024) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Volker J. Sorger, Nicola Peserico, Hangbo Yang, and Russell Schwartz "Photonic-electronic ICs for machine intelligence: devices, architectures, chip packaging", Proc. SPIE PC13118, Emerging Topics in Artificial Intelligence (ETAI) 2024, PC131180F (4 October 2024); https://doi.org/10.1117/12.3028777
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KEYWORDS
Packaging

Photonic integrated circuits

Optoelectronics

Prototyping

Waveguides

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