This presentation covers the opportunities and challenges of photonic-electronic chip-based machine intelligence acceleration hardware. We will start with a review of device-level component performance specifications such as footprint, energy consumption, reconfiguration speed, for instance. Emerging materials, when integrated monolithically into photonic waveguide circuits, show promise for next generation opto-electronic components offering high FOMs, however have high barrier to entry in for foundry PDKs. Beyond devices, we will explore a variety of architectural choices, known as co-design optimization. Parallelization strategies, smart routing, optical hardware function implementation (e.g. Fourier transformation on-chip) will be covered. Next, we explore chip packaging options including ADK and digital-twin hardware in the loop optimizations thereof. Finally, examples of prototyping will be shared and application options discussed.
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