ROIC with on-chip sigma-delta AD converter for HgCdTe e-APD FPA

Guoqiang Chen; Junling Zhang; Pan Wang; Jie Zhou; Lei Gao; Ruijun Ding

doi:10.1117/12.2035479

10 October 2013 ROIC with on-chip sigma-delta AD converter for HgCdTe e-APD FPA

Guoqiang Chen, Junling Zhang, Pan Wang, Jie Zhou, Lei Gao, Ruijun Ding

Proceedings Volume 8916, Sixth International Symposium on Precision Mechanical Measurements; 89163B (2013) https://doi.org/10.1117/12.2035479
Event: Sixth International Symposium on Precision Mechanical Measurements, 2013, Guiyang, China

Abstract

HgCdTe electron injection avalanche photodiodes (e-APDs) work at linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism and it has been demonstrated to be one of the most promising methods to focal-plane arrays (FPAs) for low-flux like hyper-spectral imaging and high-speed applications such as active imaging. This paper presents the design of a column-shared ADC for cooled e-APDs FPA. Designing a digital FPA requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures sigma-delta conversion is a promising solution for high-performance and medium size FPA such as 128×128. The performance of Sigma-delta ADC rather relies on the modulator structure which set over-sampling and noise shaping characteristics than on critical analog circuits. This makes them quite robust and flexible. A multistage noise shaping (MASH) 2-1 single bit architecture sigma-delta conversion with switched-capacitor circuits is designed for column-shared ADC, which is implanted in the GLOBALFOUNDRIES 0.35um CMOS process with 4-poly and 4-metal on the basis of a 100um pixel pitch. It operates under 3.3V supply and the output range of the quantizer is 2V. A quantization noise subtraction circuit in modulator is designed to subtract the quantization noise of first-stage modulator. The quantization noise of the modulator is shaped by a high-pass filter. The silicon area and power consumption are mainly determined by the decimation low pass filter. A cascaded integrator-comb (CIC) filter is designed as the digital decimator filter. CIC filter requires no multipliers and use limited storage thereby leading to more economical hardware implementation. The register word length of the filter in each stage is carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5V. Simulation results show that the modulator achieves the resolution higher than 12bits and 2.4mW power consumption per ADC at 7.7k Samples/s rate.

Citation Download Citation

Guoqiang Chen, Junling Zhang, Pan Wang, Jie Zhou, Lei Gao, and Ruijun Ding "ROIC with on-chip sigma-delta AD converter for HgCdTe e-APD FPA", Proc. SPIE 8916, Sixth International Symposium on Precision Mechanical Measurements, 89163B (10 October 2013); https://doi.org/10.1117/12.2035479

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
10 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Modulators

Digital filtering

Staring arrays

Readout integrated circuits

Capacitance

Sinc filters

Linear filtering

Show All Keywords

Keywords/Phrases

Search In:

Publication Years