Fault tolerant architectures by partial reconfiguration

Luis Andrés Cardona; Yi Guo; Carles Ferrer

doi:10.1117/12.2017594

28 May 2013 Fault tolerant architectures by partial reconfiguration

Luis Andrés Cardona, Yi Guo, Carles Ferrer

Proceedings Volume 8764, VLSI Circuits and Systems VI; 87640M (2013) https://doi.org/10.1117/12.2017594
Event: SPIE Microtechnologies, 2013, Grenoble, France

Abstract

The utilization of SRAM-based FPGAs in the implementation of embedded systems is in continuous growth. The flexibility that these devices offer in terms of hardware re-programming can be also a critical point to take into account when designing fault tolerant systems. As configuration values are stored in volatile memory, any event that affects this configuration memory can lead to undesirable changes in the circuits and as a consequence, erroneous outcomes can be obtained. This paper presents an approach to add fault tolerance in an aerospace application implemented in a commercial-off-the shelf FPGA (Virtex-5). By using this device, the partial reconfiguration facility can be exploited. This feature allows us to get more flexibility in hardware management at run-time also as a mean to correct specific parts of the system when faults are detected. Results regarding influence in area by using different approaches are presented.

Citation Download Citation

Luis Andrés Cardona, Yi Guo, and Carles Ferrer "Fault tolerant architectures by partial reconfiguration", Proc. SPIE 8764, VLSI Circuits and Systems VI, 87640M (28 May 2013); https://doi.org/10.1117/12.2017594

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