Digital Circuit Analysis of Insulated Shallow Extension Silicon On Void (ISESOV) FET for Low Voltage Applications

Vandana Kumari; Manoj Saxena; R. S. Gupta; Mridula Gupta

doi:10.1117/12.925533

15 October 2012 Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications

Vandana Kumari, Manoj Saxena, R. S. Gupta, Mridula Gupta

Author Affiliations +

Proceedings Volume 8549, 16th International Workshop on Physics of Semiconductor Devices; 854905 (2012) https://doi.org/10.1117/12.925533
Event: 16th International Workshop on Physics of Semiconductor Devices, 2011, Kanpur, India

Abstract

This paper investigates the potential of ISESOV architecture for low-voltage digital applications. A circuit analysis is performed for ISESOV MOSFET in terms of voltage transfer curve (VTC), supply current and noise margin and switching speed. These results are also compared with the ISE, SOV and bulk MOSFET architectures. Further improvement in the characteristic of inverter in terms of VTC and noise margin is observed by incorporating the gate stack architecture. The impact of Dual Material Gate architecture on the inverter performance has been also studied through exhaustive device simulations and it can be concluded that. ISESOV is a promising candidate for future digital applications as compared to ISE, SOV and bulk because it combines the advantages of both ISE and SOV architectures.

Citation Download Citation

Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta "Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications", Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854905 (15 October 2012); https://doi.org/10.1117/12.925533

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